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參數(shù)資料
| 型號(hào)： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 6/96頁(yè) |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-6
MD400171/C
1.0 Pin Description (continued)
Pin #
67
Pin Name
CLRTXERR
I/O
I
Description
Clear Transmit Error Input.
1 = TXRET_[1:4] Pin for Selected Port is Cleared Low
0 = Not Cleared
This input is clocked in on rising edges of the system clock, SCLK .
Flow Control Input.
132
140
148
156
FCNTRL_1
FCNTRL_2
FCNTRL_3
FCNTRL_4
I
In Half Duplex Mode:
1 = JAM Packet Transmitted When Receive Data Detected.
0 = Normal Operation
In Full Duplex Mode:
1 = MAC Control Pause Frames Transmitted When Receive Data
Detected.
0 = Normal Operation
These inputs, one per port, are clocked in on rising edges of the system
clock, SCLK .
PHY Interface (MII and 10 Mbps Serial)
180
TXC_1
203
TXC_2
226
TXC_3
249
TXC_4
175
TXEN_1
198
TXEN_2
221
TXEN_3
244
TXEN_4
176 177
TXD[3:0]_1
178 179
199 200
TXD[3:0]_2
201 202
222 223
TXD[3:0]_3
224 225
245 246
TXD[3:0]_4
247 248
183
RXC_1
206
RXC_2
229
RXC_3
252
RXC_4
193
CRS_1
216
CRS_2
239
CRS_3
6
CRS_4
191
RXDV_1
214
RXDV_2
237
RXDV_3
4
RXDV_4
I
Transmit Clock Input.
These inputs, one per port, clock out the
transmit data on TXD[3:0]_[1:4] and TXEN_[1:4] to an external Physical
Layer device on rising edges of this clock in MII mode, and on falling
edges of the clock in 10 Mbps Serial mode.
Transmit Enable Output.
These outputs, one per port, are asserted
active high to indicate that data on TXD[3:0] for that port is valid.
These outputs are clocked out on rising edges of TXC_[1:4] in MII mode
and falling edges in 10 Mbps Serial Mode.
Transmit Data Output.
These outputs, one per port, contain nibble
wide transmit data to an external Physical Layer device and are clocked
in on rising edges of TXC_[1:4] in MII Mode. In 10 Mbps Serial mode,
only TXD0 is used and data is clocked in on falling edges of TXC_[1:4].
O
O
I
Receive Clock Input.
These inputs, one per port, clock in receive data
on RXD[3:0]_[1:4], RXDV_[1:4], and RXER_[1:4] from an external
Physical Layer device on rising edges of this clock.
I
Receive Carrier Sense Input.
These inputs, one per port, have to be
asserted active high to indicate that receive data has been detected
on the Physical Layer device for that port.
I
Receive Data Valid Port 1 Input.
These inputs, one per port, have to
be asserted active high on rising edges of RXC_[1:4] to indicate when
receive data is valid on RXD[3:0]_[1:4]. This pin is not used in 10 Mbps
Serial mode.
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