參數(shù)資料
型號： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁數(shù)： 20/96頁
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-20
MD400171/C
The reception of MAC Control frames s unaffected by any
of the unicast packet address filtering functions and is
controlled by other bits described in the MAC Control
Frame section.
Multicast Address Filter
Multicast packets can be filtered by processing the desti-
nation address with the multicast address filter function.
The multicast address filter function computes the CRC on
the incoming DA and produces a 6-bit number that is
compared against the 64 values stored in the eight Hash
Filter 0-7 Registers. When the multicast packet destina-
tion address passes the address filter, the packet is
deemed valid and passed to the receive FIFO; otherwise,
the packet is rejected.
The multicast address filter requires 64 address filter bits
to be written into the Hash Filter 0-7 Registers. The
multicast address filtering algorithm is as follows:
(1) Compute a separate 32-bit CRC on
the destination address field using the
same IEEE 802.3 defined method that
computes the transmit CRC.
(2) Use bits 0-3 of the destination
address FCS to select one of the bytes
in the 64-bit address filter, as shown
in Table 4.
(3) Use bits 4-6 of the destination
address FCS to select one of the bits
within the byte selected in (2) as
shown in Table 4.
(4) If the bit selected in (3) is a “1”, the
destination address passes the filter;
otherwise, the address fails the filter
and the packet is rejected and
discarded.
Note that f all 64-bits of the address filter are programmed
to all 1’s, then the address filter passes all multicast
addresses.
The Hash filter function is normally disabled. It can be
enabled by setting the receive hash filter enable bit in the
Configuration 2 register.
The device can be programmed to reject all multicast
packets, regardless of their address, by appropriately
setting the receive address match select bits in the RX
Command register.
The reception of MAC Control frames s unaffected by any
of the multicast packet address filtering functions and is
RECEIVE MAC
General
The receive MAC (Media Access Control) section decom-
poses Ethernet packets received from the receive MII by
(1) stripping off the preamble & SFD, (2) stripping off the
CRC, (3) checking the destination address against the
address filters to determine packet validity, (4) checking
frame validity against the discard conditions, and (5)
checking the length/type field for MAC Control frames.
Each of the above operations can be ndividually disabled,
if desired. The receive MAC then sends any valid data to
the receive FIFO for storage. The status of the ast packet
received is available in the RX Status register.
Preamble & SFD Stripping
The receive MAC strips the preamble and SFD from all
receive packets before they are sent to the receive FIFO
for storage.
CRC Stripping
The receive MAC normally strips the FCS from the receive
packet. The device can be programmed to not strip the
FCS field by setting the receive CRC enable bit in the
Configuration 1 register. When this bit is set, the last 4-
bytes of he packet containing he CRC value are eft on he
receive packet and are stored in the receive FIFO as part
of the packet.
Unicast Address Filter
Unicast packets are filtered by comparing the destination
address of the receive packet against the 48-bit value
stored in the six Station Address 0-5 registers. When the
destination address of a unicast packet matches the value
stored in these Station Address registers, the unicast
packet is deemed valid and passed to the receive FIFO;
otherwise, the packet is rejected. The correspondence
between the bits in the Station Address Registers and the
incoming bits in the destination address of the receive
packet s defined n the Station Address Register definition
table.
The device can be programmed to disable the unicast
address filter function and reject all unicast packets, re-
gardless of their address, by appropriately setting the
receive address match select bits in the RX Command
register.
The device can also be programmed to ignore the last 4
bits of the receive destination address when comparing
the DA to the SA for unicast packets. This mode can be
enabled by setting the group address mode enable bit in
the Configuration 1 register.
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