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參數(shù)資料
| 型號(hào)： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 7/96頁(yè) |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-7
MD400171/C
Register Interface
17
ENREGIO
I
Enable Register I/O Operation Input.
This input must be asserted
active low to enable reading and writing of data on the Register Interface
input and output signals. This input is clocked in on falling edges of
WR and RD.
Write Strobe Input.
This input is a write enable input signal which has
to be asserted active low in order for data to be written into the addressed
register for a given port.
Read Strobe Input.
This input is a read enable input signal which has to
be asserted active low in order for data to be read from the addressed
register for a given port. This input must remain asserted until data is
outputted onto CDST[15:0] or until the READY output is asserted.
Register Port Select Input.
These inputs determine which port’s
registers are being accessed over the Register Interface. These inputs
are clocked in on falling edges of WR and RD.
11
WR
I
12
RD
I
15
16
REGPS1
REGPS0
I
11 = Port 4 Accessed Over Register Interface
10 = Port 3 Accessed Over Register Interface
01 = Port 2 Accessed Over Register Interface
00 = Port 1 Accessed Over Register Interface
Register Select Address Input.
These inputs provide the address for
the specific internal register to be accessed for a selected port. These
inputs are clocked in on falling edges of WR and RD.
Note:
Pin #21 = A7, Pin # 28 = A0
21 22 23
24 25 26
27 28
A[7:0]
I
Pin #
187 186
185 184
210 209
208 207
233 232
231 230
256 255
254 253
190
213
236
3
194
217
240
7
Management Interface (MI)
170
MDC
Pin Name
RXD[3:0]_1
I/O
I
Description
Receive Data Port 1 Input.
These inputs, one per port, contain receive
nibble wide receive data from an external Physical Layer device and are
clocked in on rising edges of RXC_[1:4] in MII mode. In 10 Mbps Serial
Mode, only RXD0 is used and data is clocked out on falling edges of
RXC_[1:4].
RXD[3:0]_2
RXD[3:0]_3
RXD[3:0]_4
RXER_1
RXER_2
RXER_3
RXER_4
COL_1
COL_2
COL_3
COL_4
I
Receive Data Error Input.
These inputs, one per port, indicate that an
external Physical Layer device has detected a symbol error. This input
is clocked in on rising edges of RXC_[1:4]. This pin is not used in
10 Mbps Serial mode.
Collision Input.
These inputs, one per port, indicate that an external
Physical Layer device has detected a collision between transmit and
receive data.
I
O
Management Interface (MI) Clock Output.
This MI clock shifts
serial data in and out of MDIO on rising edges from an external Physical
Layer device.
Management Interface (MI) Data I/O.
This bidirectional pin contains
serial data that is clocked in and out on rising edges of the MDC clock
from an external Physical Layer device.
171
MDIO
I/O
1.0 Pin Description (continued)
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