參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 26/96頁(yè)
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-26
MD400171/C
PHY INTERFACE
General
The PHY Interface provides the connection between the
84302 and an external Physical Layer device. There are
two PHY Interfaces on the 84302: (1) MII, and (2) 10 Mbps
Serial. The MII (short or Media ndependent nterface) will
operate n both 100 and 10 Mbps modes and meets all the
requirements outlined in IEEE 802.3 Clause 22. The 10
Mbps Serial Interface only operates at 10 Mbps and is
compatible with common ndustry standards for the 7-wire
serial interface. The selection of either MII or 10Mbps
serial interface is done by appropriately setting the PHY
interface select bit in the TX command register. The
device can directly connect, without any external logic, to
any Physical Layer device which complies with the either
IEEE 802.3 Clause 22 or the common 7-wire 10 Mbps
interface.
Data Format and Bit Order
The format and bit order of the MII and 10 Mbps serial data
word on TXD[3:0] and RXD[3:0] and its relationship to the
MAC frame and the System Interface data words s shown
in Figure 4 (for MII, this s same format as specified n IEEE
802.3 Clause 22). Note that Figure 4 has the device n the
little endian format (default). If the device is in the big
endian format, the byte order of the System Interface data
word s flipped. See the System Interface section for more
details if needed.
MII Signals
The MII consists of fifteen signals per port: one transmit
clock input (TXC), four transmit data outputs (TXD[3:0]),
one transmit enable output (TXEN), one receive clock
input (RXC), four receive data inputs (RXD[3:0]), one
carrier sense input (CRS), one receive data valid input
(RXDV), one receive data error input (RXER), and one
collision input (COL). The transmit and receive clocks
operate at 25 MHz in 100 Mbps mode and 2.5 MHz in 10
Mbps mode.
MII Transmit Operation
On the transmit side, TXC needs to be continuously input
at a frequency of 25 MHz in 100 Mbps mode and 2.5 MHz
in 10 Mbps mode. When no data is to be transmitted,
TXEN is deasserted, TXER is held low, and TXD[3:0] are
held low. When packet data is to be transmitted, TXEN is
asserted on the rising edge of TXC, and data on TXD[3:0]
is clocked out on rising edges of he TXC clock output while
TXEN s asserted active high. TXD[3:0] nput data s nibble
wide packet data whose format needs to be the same as
specified in IEEE 802.3 and shown in Figure 4. To
terminate the transmission of a packet, TXEN is
deasserted on the the same rising edge of TXC as the last
data nibble.
MII Receive Operation
On the receive side, RXC needs to be continuously input
at a frequency of 25 MHZ n 100 Mbps mode and 2.5 MHZ
in 10 Mbps mode. When data not being sent from an
external Physical Layer device, CRS has to be input low,
RXDV has to be input low, RXER has to be input low, and
any data on RXD[3:0] is ignored. An external Physical
Layer device signals the start of a packet to the device by
asserting CRS and holding t asserted for the entire packet
reception. While CRS is asserted, valid data is indicated
to the device when RXDV is asserted on the falling edge
of RXC. While RXDV is asserted, data on RXD[3:0] is
considered valid and input to the receive MAC on falling
edges of RXC. The RXD[3:0] data has the same frame
structure as the TXD[3:0] data and is specified in IEEE
802.3 and shown n Figure 4. The end of packet s detected
when CRS and RXDV are deasserted.
RXER is a receive error input which is asserted by the
external Physical Layer device when it detects an error on
a data nibble. RXER s asserted on he alling edge of RXC
for the duration of the RXC clock cycle during which the
nibble containing the error s being nput on RXD[3:0]. Per
IEEE 802.3 specifications, packets with containing
RXER’s are treated as if the FCS value is incorrect.
The collision nput, COL, s asserted by the Physical Layer
device whenever it detects the collision condition.
10 Mbps Serial Interface
The 10 Mbps Serial Interface uses only 7 pins in contrast
to the 15 pin MII. The 10 Mbps Serial Interface only
operates at 10 Mbps. The 10 Mbps serial mode s selected
by setting the PHY interface select bit in TX command
register. The 10 Mbps Serial nterface s dentical o he MII
at 10 Mbps except: (1) TXC and RXC frequency s 10 MHz
instead of 2.5 MHZ, (2) Data is serial wide using only data
pins RXD0 and TXD0 instead of nibble wide, (3) RXDV is
not used, (4) RXER is not used, and (5) the transmit data
signals are referenced to TXC falling edge nstead of rising
edge.
Clock Frequency Sense
As stated earlier, TXC must be continously input at a
frequency of 25 MHz n 100 Mbps mode and 2.5 MHz n 10
Mbps mode. The TXC frequency is monitored by an
internal clock frequency sense circuit and the detected
TXC frequency s stored n the TXC frequency detect bit n
the Miscellaneous Status register.
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