E
82371AB (PIIX4)
65
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
4.1.19.
GENCFG—GENERAL CONFIGURATION REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
B0–B3h
0000h
Read/Write
This register provides general system configuration for PIIX4, including signal and GPIO selects, ISA/EIO select,
IDE signal configuration, and IDE signal enables.
Bit
Description
31
KBCCS#/GPO26 Signal Pin Select.
0=KBCCS# signal (default).
1=GPO26.
This bit selects the
functionality multiplexed onto the KBCCS# pin.
30
RTCALE/GPO25 Signal Pin Select.
0=RTCALE signal (default). 1=GPO25. This bit selects the
functionality multiplexed onto the RTCALE pin.
29
RTCCS#/GPO24 Signal Pin Select.
0=RTCCS# signal (default). 1=GPO2. This bit selects the
functionality multiplexed onto the RTCCS# pin.
28
XOE# and XDIR#/GPO[22:23] Signal Pin Select.
0=XOE# and XDIR# signals (default).
1=GPO[23] and GPO[22], respectively. This bit selects the functionality multiplexed onto the XOE#
and XDIR# pins.
27
Ring Indicate (RI#)/GPI12 Signal Pin Select.
0=RI# signal (default). 1=GPI12. This bit selects the
functionality multiplexed onto the RI# pin.
26
Reserved.
25
LID/GPI10 Signal Pin Select.
0=LID signal (default). 1=GPI10. This bit selects the functionality
multiplexed onto the LID pin.
24
BATLOW#/GPI9 Signal Pin Select.
0=BATLOW# signal (default). 1=GPI9. This bit selects the
functionality multiplexed onto the BATLOW# pin.
23
THRM#/GPI8 Signal Pin Select.
0=THRM# signal (default). 1=GPI8. This bit selects the
functionality multiplexed onto the THRM# pin.
22
SUS_STAT2#/GPO21 Signal Pin Select.
0=SUS_STAT2# signal (default). 1=GPO21. This bit
selects the functionality multiplexed onto the SUS_STAT2# pin.
21
SUS_STAT1#/GPO20 Signal Pin Select.
0=SUS_STAT1# signal (default). 1=GPO20. This bit
selects the functionality multiplexed onto the SUS_STAT1# pin.
20
ZZ/GPO19 Signal Pin Select.
0=ZZ signal (default). 1=GPO19. This bit selects the functionality
multiplexed onto the ZZ pin.
19
PCI_STP#/GPO18 Signal Pin Select.
0=PCI_STP# signal (default). 1=GPO18. This bit selects the
functionality multiplexed onto the PCI_STP# pin.
18
CPU_STP#/GPO17 Signal Pin Select.
0=CPU_STP# signal (default). 1=GPO17. This bit selects
the functionality multiplexed onto the CPU_STP# pin.
17
SUSB# and SUSC#/GPO[15:16] Signal Pin Select.
0=SUSB# and SUSC# signals (default).
1=GPO15 and GPO16 respectively. This bit selects the functionality multiplexed onto the SUSB#
and SUSC# pins.