82371AB (PIIX4)
E
4
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
CONTENTS
PAGE
1.0. ARCHITECTURAL OVERVIEW....................................................................................................................12
2.0. SIGNAL DESCRIPTION................................................................................................................................15
2.1. PIIX4 Signals ..............................................................................................................................................16
2.1.1. PCI Bus Interface.................................................................................................................................16
2.1.2. ISA Bus Interface.................................................................................................................................18
2.1.3. X-Bus Interface....................................................................................................................................21
2.1.4. DMA Signals........................................................................................................................................23
2.1.5. Interrupt Controller/APIC Signals.........................................................................................................24
2.1.6. CPU Interface Signals .........................................................................................................................26
2.1.7. Clocking Signals..................................................................................................................................28
2.1.8. IDE Signals..........................................................................................................................................28
2.1.9. Universal Serial Bus Signals ...............................................................................................................33
2.1.10. Power Management Signals..............................................................................................................33
2.1.11. General Purpose Input and Output Signals.......................................................................................35
2.1.12. Other System and Test Signals.........................................................................................................39
2.1.13. Power and Ground Pins.....................................................................................................................39
2.2. Power Planes..............................................................................................................................................40
2.3. Power Sequencing Requirements..............................................................................................................41
3.0. REGISTER ADDRESS SPACE.....................................................................................................................42
3.1. PCI/ISA Bridge Configuration.....................................................................................................................42
3.1.1. PCI Configuration Registers (Function 0)............................................................................................43
3.1.2. IO Space Registers .............................................................................................................................44
3.2. IDE Configuration........................................................................................................................................47
3.2.1. PCI Configuration Registers (Function 1)............................................................................................47
3.2.2. IO Space Registers .............................................................................................................................48
3.3. Universal Serial Bus (USB) Configuration..................................................................................................48
3.3.1. PCI Configuration Registers (Function 2)............................................................................................48
3.3.2. IO Space Registers .............................................................................................................................49
3.4. Power Management Configuration .............................................................................................................50
3.4.1. IO Space Registers .............................................................................................................................51
4.0. PCI TO ISA/EIO BRIDGE REGISTER DESCRIPTIONS..............................................................................53
4.1. PCI to ISA/EIO Bridge PCI Configuration Space Registers (PCI Function 0)............................................53
4.1.1. VID—Vendor Identification Register (Function 0)................................................................................53
4.1.2. DID—Device Identification Register (Function 0)................................................................................53
4.1.3. PCICMD—PCI Command Register (Function 0) ................................................................................54
4.1.4. PCISTS—PCI Device Status Register (Function 0)............................................................................55
4.1.5. RID—Revision Identification Register (Function 0).............................................................................55