82371AB (PIIX4)
E
10
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
8.9.1.4. Control Register D ......................................................................................................................187
8.9.2. RTC Update Cycle.............................................................................................................................188
8.9.3. RTC Interrupts...................................................................................................................................188
8.9.4. Lockable RAM Ranges......................................................................................................................188
8.9.5. RTC External Connections................................................................................................................188
8.10. X-Bus Support ........................................................................................................................................188
8.11. Reset Support.........................................................................................................................................189
8.12. Stand-Alone I/O APIC Support...............................................................................................................190
9.0. IDE CONTROLLER FUNCTIONAL DESCRIPTION ..................................................................................191
9.1. IDE Signal Configuration...........................................................................................................................191
9.2. ATA Register Block Decode.....................................................................................................................192
9.3. PIO IDE Transactions...............................................................................................................................193
9.4. Bus Master Function.................................................................................................................................195
9.5. “Ultra DMA/33” Synchronous DMA Operation..........................................................................................197
10.0. USB HOST CONTROLLER FUNCTIONAL DESCRIPTION ...................................................................199
11.0. POWER MANAGEMENT FUNCTIONAL DESCRIPTION .......................................................................201
11.1. Power Management Overview ...............................................................................................................201
11.2. Clock Control..........................................................................................................................................202
11.2.1. Host Clock Control Mechanisms.....................................................................................................202
11.2.2. Stop Clock and Deep Sleep State Example Sequence...................................................................208
11.2.3. PCI Clock Control............................................................................................................................210
11.3. Peripheral Device Management .............................................................................................................210
11.3.1. Device Idle Timer.............................................................................................................................211
11.3.2. Device Trap .....................................................................................................................................212
11.3.3. Peripheral Device Management Sequence.....................................................................................212
11.3.4. Device Location on PCI Bus or ISA Bus .........................................................................................212
11.3.5. Device Specific Details....................................................................................................................215
11.3.5.1. Device 0: IDE Primary Drive 0..................................................................................................215
11.3.5.2. Device 1: IDE Primary Drive 1..................................................................................................216
11.3.5.3. Device 2: IDE Secondary Drive 0.............................................................................................216
11.3.5.4. Device 3: IDE Secondary Drive 1.............................................................................................217
11.3.5.5. Device 4: Audio.........................................................................................................................218
11.3.5.6. Device 5: Floppy Disk Drive .....................................................................................................219
11.3.5.7. Device 6: Serial Port A..............................................................................................................220
11.3.5.8. Device 7: Serial Port B..............................................................................................................221
11.3.5.9. Device 8: LPT (Parallel Port)....................................................................................................222
11.3.5.10. Device 9: Generic I/O Device 0..............................................................................................223
11.3.5.11. Device 10: Generic I/O Device 1............................................................................................224
11.3.5.12. Device 11: User Interface (Keyboard, Mouse, Video)............................................................225
11.3.5.13. Device 12: Cardbus Slot (or Generic I/O and MEM Device)..................................................226
11.3.5.14. Device 13: Cardbus Slot (or Generic I/O and MEM Device)..................................................227