
82371AB (PIIX4)
E
264
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Global Standby Timer Expiration:
[GSTBY_EN]
[GSTBY_STS]
— The Global Standby Timer will set the [GSTBY_STS] bit upon expiration, and if enabled will
generate an SMI#. It can also be used to generate a suspend state resume events. See
below for more information on Global Standby Timer operation.
PCI Bus Master Requests:
[BM_TRP_EN]
[BM_STS]
— Assertion of PCIREQ[0:3] or PHOLD#, signifying PCI Master activity will generate an SMI#
if enabled. This can also cause idle, burst, or global standby timer reloads as part of Device
8 Monitor logic.
APMC Control Register Write:
[APMC_EN]
[APM_STS]
— Writes to the APM Control Register (APMC, IO port B2h) generate an SMI#, if enabled.
USB Legacy Keyboard/Mouse
:
[LEGACY_USB_EN]
[LEGACY_USB_STS]
— The USB Legacy Keyboard logic uses SMI# generation as part of its operation. See the
“USB Host Controller Functional Description” section and the “Universal Host Controller
Interface Design Guide” document for additional information concerning USB Legacy
Keyboard. The [LEGACY_USB_EN] bit must be set active in order for USB Legacy
Keyboard to function.
Software Timer SMI:
[IDL_EN_DEV3]
[IDL_RLD_EN_DEV3]
[IDL_STS_DEV3]
— The Idle Timer for Device 3 Monitoring can be used as a Software SMI Timer. If the Idle
timer reload events are disabled (via [IDL_RLD_EN_DEV3] bit), the timer will count down
without reload and its expiration will generate an SMI#. See the “Peripheral Device
Management” section for more information on idle timer operation.
Device Monitor Trap:
[TRP_EN_DEVx]
x=0–13
[TRP_STS_DEVx]
[DEV_STS]
— The IO Traps for Device Monitoring subsystem generate an SMI# when the programmed
trap event occurs. The [DEV_STS] bit is logical “OR” of [TRP_STS_DEVx] and
[IDL_STS_DEVx] bits. See the “Peripheral Device Management” section for more
information on device monitor idle timer operation.
Device Monitor Idle Timer Expiration:
[IDL_EN_DEVx]
[IDL_STS_DEVx]
[DEV_STS]
x=0–11
— The Idle Timers for Device Monitoring subsystem count down and generate an SMI# upon
expiration, if enabled. The [DEV_STS] bit is logical “OR” of [TRP_STS_DEVx] and
[IDL_STS_DEVx] bits. See the “Peripheral Device Management” section for more
information on device monitor idle timer operation.
PIIX4 Master Abort on PCI
[P4MA_EN]
[PM4A_STS]
— If enabled, a Master Abort to a PIIX4 initiated PCI cycle will generate an SMI#.