參數(shù)資料
型號(hào)： 5962-9162303MXC
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CPGA145
封裝： CERAMIC, PGA-145
文件頁數(shù)： 79/98頁
文件大小： 1546K
代理商： 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
local-bus timing: bus control inputs (see Note 5 and Figure 48)
NO
34020A-32
34020A-40
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
57
td(CK2H-ALL)
Delay time, ALTCH low after LCLK2 no
longer low
tQ+15
tQ+13.5
ns
58
td(CK1L-ALH)
Delay time, ALTCH high after LCLK1 no
longer high
tQ+15
tQ+13.5
ns
59
td(CK1H-LAV)
Delay time, LAD0--LAD31 address valid
after LCLK1 no longer low
tQ+22
tQ+20
ns
60
th(LAV-CK2L)
Hold time, LAD0--LAD31 address valid after
LCLK2 low
tQ--15+ s
tQ--12+ s
ns
61
td(CT-LAD)
Delay time, LAD0--LAD31 driven after
earlier of DDIN no longer high or CAS no
longer low or TR/QE no longer low
tQ--5+ s *
ns
62
th(LAV-CTV)
Hold time, LAD0--LAD31 read data valid
after earlier of DDIN low or RAS,CAS,or
TR/QE low
3.5
ns
63
td(CK2L-LAV)
Delay time, LAD0--LAD31 data valid after
LCLK2 no longer high (write)
tQ+22+ s
tQ+20+ s
ns
64
th(CK2L-LAV)
Hold time, LAD0--LAD31 data valid after
LCLK2 low (write)
tQ--15
tQ--13.5
ns
65
td(CK1H-RCV)
Delay time, RCA0--RCA12 row address
valid after LCLK1 no longer low
tQ+22
ns
66
td(CK2L-RCV)
Delay time, LAD0--LAD31 column address
valid after LCLK2 no longer high
tQ+22+ s
tQ+20+ s
ns
67
th(RCV-CK2L)
Hold time, RCA0-RCA12 address valid after
LCLK2 low
tQ--15
tQ--13.5
ns
68
td(CK1H-DIH)
Delay time, DDIN high after LCLK1 no longer
low
tQ+15
tQ+13.5
ns
69
td(CK1L-DIL)
Delay time, DDIN low after LCLK1 no longer
high
tQ+15
tQ+13.5
ns
70
td(CK1H-DOL)
Delay time, DDOUT low after LCLK1 no
longer low
tQ+15
tQ+13.5
ns
71
td(CK1L-DOH)
Delay time, DDOUT high after LCLK1 no
longer high
tQ+15
tQ+13.5
ns
72
td(CK2L-DOL)
Delay time, DDOUT low after LCLK2 no
longer high
tQ+15+ s
tQ+13.5+ s
ns
73
tsu(LAV-ALL)
Setup time, LAD0--LAD31 data valid before
ALTCH no longer high
tQ--16
tQ--13.5
ns
74
ten(DAV-DIH)
Enable time, data valid after DDIN high
(see Note 10)
2tQ--20
2tQ--17
ns
75
tdis(DAV-DIL)
Disable time, data in the high-impedance
state after DDIN low (see Note 10)
tQ--12+ s *
tQ--10+ s *
ns
* The parameter is not production tested.
NOTES: 4. s =tQ if using the clock stretch;
s = 0 otherwise
10. DDIN is used to control LAD bus buffers between the SMJ34020A and local memory. Parameter 74 references the time for these
data buffers to go from the high-impedance state to an active level. Parameter 75 references the time for the buffers to go from an
active level to the high-impedance state.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962-9162304MYA 制造商:Texas Instruments 功能描述:2ND GENERATION GRAPHICS SIGNAL PROCESSOR - Rail/Tube
5962-9162501HXA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H - Rail/Tube
5962-9162501HZA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H - Rail/Tube
5962-9162502HXA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H, SLAVE - Rail/Tube
5962-9162502HZA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H, SLAVE - Rail/Tube
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