參數(shù)資料
型號(hào): 5962-9162303MXC
廠商: TEXAS INSTRUMENTS INC
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, CPGA145
封裝: CERAMIC, PGA-145
文件頁數(shù): 37/98頁
文件大?。?/td> 1546K
代理商: 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
The VRAM cycle shown in Figure 21 is issued in any of three ways:
D
Pixel operation instruction with CST in DPYCTL set
D
Horizontal blank reload cycle requested by the video-control logic with VCE in DPYCTL cleared
D
Video timeout due to SCOUNT match with the value in MLRNXT and VCE and SSV in DPYCTL cleared
This cycle is indicated by TR/QE and SF low and CAS and WE high at the time RAS goes low. The timing of
the low-to-high transition of TR/QE is dependent upon the timing of SCLK when doing a midline reload cycle.
During the address portion of the cycle, the status on LAD0--LAD3 indicates either a video-initiated VRAM
memory-to-register transfer (status code = 0100), or a CPU-initiated VRAM memory-to-register transfer
(status code = 0101).
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