參數(shù)資料
型號(hào)： 5962-9162303MXC
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CPGA145
封裝： CERAMIC, PGA-145
文件頁(yè)數(shù)： 17/98頁(yè)
文件大小： 1546K
代理商： 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
enabling clock stretch (continued)
READ
ADDR
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
READ
ADDR
4
3
2
1
4
3
1
4
3
2
4
3
2
11
2
Stretch
Stretch Mode Enabled
Stretch Mode Disabled
Figure 7. Three 32-Bit Page-Mode Reads
The stretched cycles are designed to accommodate worst-case 32-bit page-mode accesses, so during some
nonpage-mode memory accesses stretches that are not essential can be generated. For example:
WRITE
ADDR
READ
ADDR
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
WRITE
ADDR
READ
ADDR
4
3
2
1
4
3
4
3
2
4
3
2
11
2
Stretch
Stretch Mode Enabled
Stretch Mode Disabled
1
Stretch
Figure 8. One 32-Bit Nonpage-Mode Read-Write
Stretches are inserted in read-modify-write accesses to help ease bus turn-around timings. In the above
example, the second stretch is not needed to help these timings because the read/write turn-around has the
whole of the address cycle to evaluate.
clock-stretch timing example, SMJ34020A-32 and 150-ns DRAMs
This example analyzes a memory interface timing parameter. It shows that the clock-stretch mechanism can
be used to allow the SMJ34020A-32 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
D
A SMJ34020A-32,
which has a 32-MHz clock input frequency and hence a 125-ns cycle time, so
tQ = 31 ns. Timing parameters are taken from this data sheet.
D
A SMJ44C251-10
1 megabit × 1 bit DRAM. Timing parameters are taken from the corresponding
Texas Instruments data sheet.
row address hold data after RAS low, th(ADV-REL)
Without clock stretch
SMJ4C1024 th(RA)
Hold time, row address valid after RAS low
Min = 20 ns
SMJ34020A Parameter 88 Hold time, row address valid after RAS low
Min = tQ -- 5 ns = 26 ns
If RAS is passed through a PAL with a delay of 7 ns, then th(RA) seen by the DRAM is 26 ns -- 7 ns = 19 ns.
This violates the 20 ns minimum.
相關(guān)PDF資料
PDF描述
5962H9215308QUX 32K X 8 STANDARD SRAM, 40 ns, DFP36
5962H9215306VMX 32K X 8 STANDARD SRAM, 60 ns, CDIP28
5962-9309104HYX 512K X 8 EEPROM 5V MODULE, 200 ns, CDIP32
5962-9458503H6X 128K X 32 EEPROM 5V MODULE, 200 ns, CPGA66
5962-9461115HTX 512K X 32 MULTI DEVICE SRAM MODULE, 20 ns, CPGA66
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962-9162304MYA 制造商:Texas Instruments 功能描述:2ND GENERATION GRAPHICS SIGNAL PROCESSOR - Rail/Tube
5962-9162501HXA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H - Rail/Tube
5962-9162501HZA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H - Rail/Tube
5962-9162502HXA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H, SLAVE - Rail/Tube
5962-9162502HZA 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H, SLAVE - Rail/Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*