參數(shù)資料
型號: 5962-9162303MXC
廠商: TEXAS INSTRUMENTS INC
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, CPGA145
封裝: CERAMIC, PGA-145
文件頁數(shù): 52/98頁
文件大?。?/td> 1546K
代理商: 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
56
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
In Figure 30, SMJ34020A provides HRDY as soon as it recognizes the host write cycle (if no other host write
cycle is in progress), allowing the host to latch the data in the external data latches. The host then attempts a
second write but does not get an immediate HRDY because the SMJ34020A is still writing the first data to
memory. As soon as the memory write completes, HRDY goes high so that the host can latch the new data. The
SMJ34020A then writes the second data while the host continues other processing. The host access request
is synchronized to the SMJ34020A at the beginning of Q4 so that the local memory cycle can begin in Q1. If
the external host access request occurs after the setup time requirement before Q4, the request is not
considered until the next Q4 cycle. During a host write cycle DDIN is active so that if the write is to the
SMJ34020A I/O registers, the data can be required within the GSP.
相關(guān)PDF資料
PDF描述
5962H9215308QUX 32K X 8 STANDARD SRAM, 40 ns, DFP36
5962H9215306VMX 32K X 8 STANDARD SRAM, 60 ns, CDIP28
5962-9309104HYX 512K X 8 EEPROM 5V MODULE, 200 ns, CDIP32
5962-9458503H6X 128K X 32 EEPROM 5V MODULE, 200 ns, CPGA66
5962-9461115HTX 512K X 32 MULTI DEVICE SRAM MODULE, 20 ns, CPGA66
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