參數(shù)資料
型號(hào)： 5962-9162303MXC
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CPGA145
封裝： CERAMIC, PGA-145
文件頁數(shù)： 63/98頁
文件大?。?/td> 1546K
代理商： 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
dc electrical characteristics over recommended range of supply voltage (see Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUSFLT, LRDY, VCLK,
PGMD SIZE16 CSYNC
GB PKG
2.2
VCC+0.3
PGMD,SIZE16,CSYNC,
VSYNC, HSYNC
HT PKG
2.3
VCC+0.3
HWRITE HREAD
GB PKG
2
VCC+0.3
VIH
High-level input
lt
HWRITE, HREAD
HT PKG
2.3
VCC+0.3
V
VIH
voltage
HA5--HA31, HCS,
GB PKG
2
VCC+0.3
V
HA5 HA31, HCS,
HBS0--HBS3
HT PKG
2.3
VCC+0.3
CLKIN only
3
VCC+0.3
All other inputs
2
VCC+0.3
VIL
Low-level input voltage, HT only: HCS VIL = -- 0.3 min, 0.7 V max
--0.3
0.8
V
VOH
High-level output voltage
VCC =MIN,
IOH =MAX
2.6
V
GB PKG
0.60
VOL
Low-level output
voltage
DDIN, HINT, HRDY, R0,R1,
EMU3
HT PKG
VCC = MAX,
I
MIN
0.8
V
VOL
voltage
HYSNC, VSYNC
HT PKG
IOL =MIN
0.8
V
All other outputs
0.6
GB PKG
VCC =MAX,
20
I
Output current leakage (high impedance)
HT PKG
VCC = MAX,
VO =2.8 V
20
A
IO
Output current, leakage (high impedance)
GB PKG
VCC =MAX,
-- 20
μA
HT PKG
VCC = MAX,
VO =0.6 V
--20
II
Input current (All inputs except EMU0--EMU2,
HREAD,HWRITE)
VI =VSS to VCC
±20
μA
I
Supply current
34020A-32
VCC =MAX,
265
mA
ICC
Supply current
34020A-40
VCC = MAX,
Freq = MAX
280
mA
Ci
Input capacitance
10
18
pF
Co
Output capacitance
18
25
pF
All typical values are at VCC =5V, TA (ambient-air temperature)= 25° C.
EMU0--EMU2 are not connected in a typical configuration. Nominal pullup current for EMU0--EMU2 and HREAD,HWRITE is 600 μA.
NOTE 4: HDST and HOE (output terminals) have internal pullup resistors that allow high logic levels to be maintained when the SMJ34020A is
not actually driving these pins.
signal transition levels
2V
(see Note A)
0.8 V
NOTE A: 2.2 V for BUSFLT, VCLK, LRDY, PGMD,SIZE16. 3V for CLKIN.
Figure 37. TTL-Level Inputs
For high-to-low and low-to-high transitions, the level at which the input timing is measured is 1.5 V.
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