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參數(shù)資料
| 型號： | 5962-9162303MXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, CPGA145 |
| 封裝： | CERAMIC, PGA-145 |
| 文件頁數(shù)： | 71/98頁 |
| 文件大?。?/td> | 1546K |
| 代理商： | 5962-9162303MXC |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
73
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
output signal characteristics (continued)
QW
QX
QY
QZ
tt(SG)
td(SG-SGV)
td(SGV-SG)
th(CK-SG)
td(CK-SGV)
th(CK-SG)
LCLKx
SIGNALa
SIGNALb
tw(SGH)
tw(SGL)
td(SGV-SG)
td(SG-SGV)
td(CK-SGV)
td(SGV-SG)
td(SG-SGV)
tt(SG)
SeeNoteA
NOTE A: Any of these quarter phases could be 2tQ if they are stretched (see clock stretch,
page 21).
Figure 42. Output Signal Characteristics
example of how to use the general output signal characteristics
Assume a system is using a SMJ34020A-32. Determine the maximum time from the start of the falling edge
of ALTCH to the time when data must be valid on LAD for a local-memory write cycle.
From the local-memory read-modify-write-cycle timing diagram (Figure 12), the time from the falling edge of
ALTCH to valid data on LAD is roughly Q3 + Q4; i.e., 2tQ. A more precise value can be obtained by using the
table of output signal characteristics.
The parameter of interest is td(SG-SGV). In Figure 42, there are two representations of td(SG-SGV) that relate
SIGNALa and SIGNALb (the third representation of this parameter relates SIGNALb to itself and is not useful
in this example). Let SIGNALa represent ALTCH because ALTCH is making a transition first. Let SIGNALb
represent LAD. By definition, the signal becoming valid (SGV) determines whether the fast value or the slow
value from the table is used.
In this case, for parameter td(SG-SGV), SGV is LAD. LAD is in the slow group, so the maximum value for td(SG-SGV)
is ntQ + 22. The value for n is 2 from the analysis of the diagram on page 28. Thus, the maximum time from the
start of the falling edge of ALTCH to the time when data must be valid on LAD for a local-memory write cycle
is 2tQ +22ns.
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| 5962H9215308QUX | 32K X 8 STANDARD SRAM, 40 ns, DFP36 |
| 5962H9215306VMX | 32K X 8 STANDARD SRAM, 60 ns, CDIP28 |
| 5962-9309104HYX | 512K X 8 EEPROM 5V MODULE, 200 ns, CDIP32 |
| 5962-9458503H6X | 128K X 32 EEPROM 5V MODULE, 200 ns, CPGA66 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9162304MYA | 制造商:Texas Instruments 功能描述:2ND GENERATION GRAPHICS SIGNAL PROCESSOR - Rail/Tube |
| 5962-9162501HXA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H - Rail/Tube |
| 5962-9162501HZA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H - Rail/Tube |
| 5962-9162502HXA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H, SLAVE - Rail/Tube |
| 5962-9162502HZA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H, SLAVE - Rail/Tube |
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