參數(shù)資料
型號(hào)： 5962-9162303MXC
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CPGA145
封裝： CERAMIC, PGA-145
文件頁數(shù)： 18/98頁
文件大?。?/td> 1546K
代理商： 5962-9162303MXC
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
row address hold data after RAS low, th(ADV-REL) (continued)
With clock stretch
SMJ34020A
Parameter 88
th(ADV-REL)
Hold time, row address valid after RAS low
Min = 2tQ -- 5 ns = 57 ns
With the same 7-ns PAL delay, the DRAM sees th(RA) as 57 ns -- 7ns = 50 ns, which does not violate the
20 ns minimum.
cycle timing examples
The following figures show examples of many of the basic cycles that the SMJ34020A uses for memory access,
VRAM control, multiprocessor bus control, and coprocessor communication. These figures should not be used
to determine specific signal timings, but can be used to see signal relationships for the various cycles. The
Q4 phases that could be stretched are marked with an * on the diagrams. The conditions required for the stretch
are:
D
The design uses a SMJ34020A.
D
The CONFIG register’s CSE bit is set to 1.
D
The SMJ34020A is doing either:
a) Any address cycle, or
b) A read data cycle in a read-modify-write sequence
The following remarks apply to memory timing in general. A row address is output on RCA0--RCA12 at the start
of a cycle along with the full address and status on LAD0--LAD31. These remain valid until after the fall of ALTCH
and RAS. The column address is then output on RCA0--RCA12, and LAD0--LAD31 are set to read or write data
for the memory access. During a write, the data and WE are set valid prior to the falling edge of CAS; the data
remains valid until after WE and CAS have returned high.
Large memory configurations can require external buffering of the address and data lines. DDIN and DDOUT
coordinate these external buffers with LAD.
During the address output to LAD by the SMJ34020A (Figure 9), the least significant four bits (LAD0--LAD3)
contain a bus-status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports
page-mode operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without
inserting wait states. DDOUT returns high after the initial address output on LAD (during Q4), indicating that
a memory read cycle is about to take place.
PAL is a trademark of Advanced Micro Devices, Inc.
相關(guān)PDF資料
PDF描述
5962H9215308QUX 32K X 8 STANDARD SRAM, 40 ns, DFP36
5962H9215306VMX 32K X 8 STANDARD SRAM, 60 ns, CDIP28
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