E
1.0
28F1602C3, 28F3204C3
5
PRODUCT PREVIEW
INTRODUCTION
This document contains the specifications for the
3 Volt Advanced+ Stacked Chip Scale Package
(Stacked-CSP) memory. These memories are
stacked memory solutions with 32-MB flash
memory and 4-MB SRAM or 16-MB flash memory
and 2-MB SRAM.
Throughout this document, the term
“2.7 V” refers
to the full voltage range 2.7 V–3.3 V (except where
noted otherwise) and “F-V
PP
=
12 V” refers to 12 V
±5%.
1.1
Product Overview
The Intel
Stacked-CSP memory provides secure
low-voltage
memory
solutions
applications. This memory family combines two
memory technologies, flash memory and SRAM, in
one package. The flash memory delivers enhanced
security features, a block locking capability that
allows instant locking/unlocking of any flash block
with zero-latency, and a 128-bit protection register
that enable unique device identification, to meet the
needs of next generation portable applications.
for
portable
Discrete supply balls provide single voltage read,
program, and erase capability at 2.7 V while also
allowing 12 V F-V
PP
for faster production flash
programming. The improved 12 V production
programming feature reduce external logic and
simplifies board designs when combining 12 V
production
programming
programming capability.
with
2.7 V
in-field
The 3 Volt Advanced+ Stacked-CSP memory
products are available in the following densities:
16-Mbit flash memories organized as 1024
Kwords of 16 bits each with 2-Mbit SRAM
memories organized as 128Kwords of 16 bits
each.
32-Mbit flash memories organized as 2048
Kwords of 16 bits each with 4-Mbit SRAM
memories organized as 256-Kwords of 16 bits
each.
The flash has eight 8-KB parameter blocks located
at either the top (denoted by -T suffix) or the bottom
(-B suffix) of the address map in order to
accommodate different microprocessor protocols
for kernel code location. The remaining flash
memory is grouped into 64-Kbyte main blocks. All
flash blocks can be locked or unlocked instantly to
provide complete protection for code or data (see
Section 6.0 for details).
The Command User Interface (CUI) serves as the
interface
between
the
microcontroller and the internal operation of the
flash memory. The flash’s internal Write State
Machine
(WSM)
automatically
algorithms and timings necessary for program and
erase operations, including verification, thereby
unburdening the microprocessor or microcontroller.
microprocessor
or
executes
the
The flash’s status register indicates the status of
the WSM by signifying block erase or word program
completion and status.
Flash program and erase automation allows
program and erase operations to be executed using
an industry-standard two-write command sequence
to the CUI. Program operations are performed in
word increments. Erase operations erase all
locations within a block simultaneously. Both
program and erase operations can be suspended
by the system software in order to read from any
other flash block. In addition, data can be
programmed to another flash block during an erase
suspend.
The 3 Volt Advanced+ Stacked-CSP memories
offer two low-power savings features: Automatic
Power Savings (APS) for flash memory and
standby mode for flash and SRAM. The device
automatically enters APS mode following the
completion of a read cycle from the flash memory.
Standby mode is initiated when the system
deselects the device by driving F-CE# and S-CS
1
#
or S-CS
2
inactive. Power savings features
significantly reduce power consumption.
The flash memory can be reset by lowering F-RP#
to GND. This provides CPU-memory reset
synchronization and additional protection against
bus noise that may occur during system reset and
power-up/down sequences.