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參數(shù)資料
| 型號： | 28F1602C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 17/62頁 |
| 文件大?。?/td> | 538K |
| 代理商： | 28F1602C3 |
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E
6.5
28F1602C3, 28F3204C3
17
PRODUCT PREVIEW
Reading a Block’s Lock Status
The lock status of every block can be read in the
configuration read mode of the device. To enter this
mode, write 90H to the device. Subsequent reads at
Block Address + 00002 will output the lock status of
that block. The lock status is represented by the
lowest two output balls, DQ
0
and DQ
1
. DQ
0
indicates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when entering
Lock-Down. DQ
1
indicates Lock-Down status and is
set by the Lock-Down command. It cannot be
cleared by software, only by device reset or power-
down.
Table 7. Block Lock Status
Item
Address
Data
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Block Is Locked-Down
XX002
LOCK
DQ
0
= 0
DQ
0
= 1
DQ
1
= 1
6.6
Locking Operation During
Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock, or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation,
first write the erase suspend command (B0H), then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired lock command sequence to a block and
the lock status will be changed. After completing
any desired lock, read, or program operations,
resume the erase operation with the Erase Resume
command (D0H).
If a block is locked or locked-down during a
suspended erase of the same block, the locking
status bits will be changed immediately, but when
the erase is resumed, the erase operation will
complete.
Locking operations cannot be performed during a
program suspend.
6.7
Status Register Error Checking
Using nested locking or program command
sequences during erase suspend can introduce
ambiguity into status register results.
Since locking changes are performed using a two
cycle command sequence, e.g., 60H followed by
01H to lock a block, following the Configuration
Setup command (60H) with an invalid command will
produce a lock command error (SR.4 and SR.5 will
be set to 1) in the status register. If a lock
command error occurs during an erase suspend,
SR.4 and SR.5 will be set to 1, and will remain at 1
after the erase is resumed. When erase is
complete, any possible error during the erase
cannot be detected via the status register because
of the previous locking command error.
A similar situation happens if an error occurs during
a program operation error nested within an erase
suspend.
7.0
FLASH MEMORY 128-BIT
PROTECTION REGISTER
The 3 Volt Advanced+ Stacked-CSP architecture
includes a 128-bit protection register than can be
used to increase the security of a system design.
For example, the number contained in the
protection register can be used to
“mate” the flash
component with other system components such as
the CPU or ASIC, preventing device substitution.
The 128-bits of the protection register are divided
into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit
number, which is unchangeable. The other segment
is left blank for customer designs to program as
desired.
Once
the
programmed, it can be locked to prevent
reprogramming.
customer
segment
is
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| 28F160C3BA90 | 制造商: 功能描述: 制造商:Intel 功能描述: 制造商:undefined 功能描述: |
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