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參數(shù)資料
| 型號： | 28F1602C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 11/62頁 |
| 文件大?。?/td> | 538K |
| 代理商： | 28F1602C3 |
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E
4.1.3
28F1602C3, 28F3204C3
11
PRODUCT PREVIEW
STANDBY
With F-CE# and S-SC
1
# or S-SC
2
inactive, the
Stacked-CSP enters a standby mode, which
substantially reduces device power consumption. In
standby, outputs are placed in a high-impedance
state independent of F-OE# and S-OE#. If the flash
is deselected during a program or erase operation,
the flash continues to consume active power until
the program or erase operation is complete.
4.1.4
RESET
The flash memory supports a reset signal,
F-RP. From read mode, F-RP# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a
high-mpedance state, and turns off all internal
circuits. After return from reset, a time t
PHQV
is
required until the initial read access outputs are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The flash device resets to read array
mode, the status register is set to 80H, and all
blocks are locked. This case is shown in Figure 8A.
If F-RP# is taken low for time t
PLPH
during a flash
program or erase operation, the operation will be
aborted and the memory contents at the aborted
location (for a program) or block (for an erase) are
no longer valid, since the data may be partially
erased or written. The abort process goes through
the following sequence: When F-RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
PLRH
to complete. After
this time t
PLRH
, the part will either reset to read
array mode (if F-RP# has gone high during t
PLRH
,
Figure 8B) or enter reset mode (if F-RP# is still
logic low after t
PLRH
, Figure 8C). In both cases,
after returning from an aborted operation, the
relevant time t
PHQV
or t
PHWL
/t
PHEL
must be waited
before a read or write operation is initiated, as
discussed in the previous paragraph. However, in
this case, these delays are referenced to the end of
t
PLRH
rather than when F-RP# goes high.
As with any automated device, it is important to
assert F-RP# during system reset. When the
system comes out of reset, processor expects to
read from the flash memory. Automated flash
memories provide status information when read
during program or block erase operations. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel
Flash memories allow
proper CPU initialization following a system reset
through the use of the F-RP# input. In this
application, F-RP# is controlled by the same
RESET# signal that resets the system CPU.
4.1.5
WRITE
Writes to flash take place when both F-CE# and
F-WE# are low and F-OE# is high. Writes to SRAM
take place when both S-CS
1
# and S-WE# are low
and S-OE# and S-SC
2
are high. Commands are
written to the flash memory’s Command User
Interface (CUI) using standard microprocessor write
timings to control flash operations. The CUI does
not occupy an addressable memory location within
the flash component. The address and data buses
are latched on the rising edge of the second F-WE#
or F-CE# pulse, whichever occurs first. Figure 7
illustrates a program and erase operation. The
available commands are shown in Table 5.
5.0
FLASH MEMORY MODES OF
OPERATION
The flash memory has four read modes: read array,
read configuration, read status, and read query.
The write modes are program and erase. Three
additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are
available only during suspended operations. These
modes
are
reached
summarized in Table 5.
using
the
commands
5.1
Read Array
When F-RP# transitions from V
IL
(reset) to V
IH
, the
device defaults to read array mode and will respond
to the read control inputs without any additional CUI
commands.
In addition, the address of the desired location must
be applied to the address balls. If the device is not
in read array mode, as would be the case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
5.2
Read Configuration
The
manufacturer/device identifier. The device is
switched to this mode by writing the read
configuration command (90H). Once in this mode,
read
configuration
mode
outputs
the
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