E
28F1602C3, 28F3204C3
3
PRODUCT PREVIEW
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION..............................................5
1.1 Product Overview.........................................5
2.0 PACKAGE BALLOUTS...................................6
3.0 STACKED CHIP SCALE PACKAGE
ORGANIZATION ............................................8
4.0 PRINCIPLES OF OPERATION .......................8
4.1 Bus Operation..............................................9
5.0 FLASH MEMORY MODES OF OPERATION 11
5.1 Read Array.................................................11
5.2 Read Configuration ....................................11
5.3 Read Status Register .................................12
5.4 Read Query................................................12
5.5 Program Mode ...........................................12
5.6 Erase Mode................................................13
6.0 FLASH MEMORY FLEXIBLE BLOCK
LOCKING .....................................................16
6.1 Locking Operation......................................16
6.2 Locked State..............................................16
6.3 Unlocked State...........................................16
6.4 Lock-Down State........................................16
6.5 Reading a Block’s Lock Status...................17
6.6 Locking Operation During Erase Suspend..17
6.7 Status Register Error Checking..................17
7.0 FLASH MEMORY 128-BIT PROTECTION
REGISTER ...................................................17
7.1 Reading the Protection Register.................18
7.2 Programming the Protection Register.........18
7.3 Locking the Protection Register..................19
8.0 FLASH MEMORY PROGRAM AND ERASE
VOLTAGES..................................................19
8.1 Improved 12 Volt Production Programming19
8.2 F-V
PP
≤
V
PPLK
for Complete Protection......19
9.0 ELECTRICAL SPECIFICATIONS..................20
9.1 Absolute Maximum Ratings........................20
9.2 Operating Conditions..................................20
9.3 Capacitance ...............................................21
9.4 DC Characteristics .....................................21
9.5 Flash AC Characteristics—Read
Operations—Extended Temperature.........25
9.6 Flash AC Characteristics—Write
Operations—Extended Temperature.........28
9.7 Flash Erase and Program Timings .............29
9.8 Flash Reset Operations..............................31
9.9 SRAM AC Characteristics—Read
Operations—Extended Temperature.........32
9.10 SRAM AC Characteristics—Write
Operations—Extended Temperature.........34
9.11 SRAM Data Retention Characteristics—
Extended Temperature..............................35
10.0 MIGRATION GUIDE INFORMATION ..........36
11.0 SYSTEM DESIGN CONSIDERATIONS.......36
11.1 Background..............................................36
11.2 Flash Control Considerations ...................37
11.3 Noise Reduction.......................................38
11.4 Simultaneous Operation...........................39
11.5 Printed Circuit Board Notes......................40
11.6 System Design Notes Summary...............40
12.0 ORDERING INFORMATION......................41
13.0 ADDITIONAL INFORMATION...................41
Appendix A: Program/Erase Flowcharts..........42
Appendix B: CFI Query Structure.....................47
Appendix C: Word-Wide Memory Map
Diagrams......................................................55
Appendix D: Device ID Table.............................57
Appendix E: Protection Register Addressing..58
Appendix F: Mechanical Specification.............59
Appendix G: Media Information........................61