參數(shù)資料
型號： 28222-13
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口
文件頁數(shù)： 88/161頁
文件大?。?/td> 1832K
代理商： 28222-13
3.0 Registers
CN8223
3.2 Control Register Overview
ATM Transmitter/Receiver with UTOPIA Interface
3-2
Conexant
100046C
Cell Generation Control - Port 2
3.2 Control Register Overview
Table 3-2
lists the 52 control registers of the CN8223. Control registers are realized as latches within the
CN8223 and are programmed by a write operation from the microprocessor. No initialization is provided for
operational purposes. All registers must be initialized as required for each application by the microprocessor. A
reset signal on the RESET pin (pin 118) resets counters and framer state machines. RESET does not affect
control register contents.
Control bits that do not have a defined function are reserved and must be written to 0. All control registers
can be read to verify contents, except those control bits whose functions cause single events and are, therefore,
not latched.
Control registers in this section have been ordered by function: 7 control configurations, 19 control
transmitter functions, 22 control receiver functions, and 4 enable interrupts.
Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (1 of 2)
Address
Name
Function
0x00
CONFIG_1
Configuration Control Register 1
0x01
CONFIG_2
Configuration Control Register 2
0x02
CONFIG_3
Configuration Control Register 3
0x03
TXFEAC_ERRPAT
Transmit FEAC/BIP-8 Error Pattern
0x04
CELL_GEN_0
Cell Generation Control - Port 0
0x05
CELL_GEN_1
Cell Generation Control - Port 1
0x06
CELL_GEN_2
0x07
CELL_GEN_3
Cell Generation Control - Port 3
0x08
TX_RATE_23
Transmit Rate Control Value - Ports 2, 3
0x09
TX_RATE_01
Transmit Rate Control Value - Ports 0, 1
0x0A
TX_IDLE_12
Transmit Idle Header Value - Octets 1, 2
0x0B
TX_IDLE_34
Transmit Idle Header Value - Octets 3, 4
0x0C
TX_HDR0_12
Transmit Port 0 Header Value - Octets 1, 2
0x0D
TX_HDR0_34
Transmit Port 0 Header Value - Octets 3, 4
0x0E
TX_HDR1_12
Transmit Port 1 Header Value - Octets 1, 2
0x0F
TX_HDR1_34
Transmit Port 1 Header Value - Octets 3, 4
0x10
TX_HDR2_12
Transmit Port 2 Header Value - Octets 1, 2
0x11
TX_HDR2_34
Transmit Port 2 Header Value - Octets 3, 4
0x12
TX_HDR3_12
Transmit Port 3 Header Value - Octets 1, 2
0x13
TX_HDR3_34
Transmit Port 3 Header Value - Octets 3, 4
0x14
CELL_VAL
Cell Validation Control
0x15
HDR_VAL0_12
Receive Port 0 Header Value - Octets 1, 2
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