參數(shù)資料
型號: 28222-13
廠商: Conexant Systems, Inc.
英文描述: ATM Transmitter/Receiver with UTOPIA Interface
中文描述: 自動柜員機發(fā)射機/接收機的UTOPIA接口
文件頁數(shù): 100/161頁
文件大?。?/td> 1832K
代理商: 28222-13
3.0 Registers
CN8223
3.4 Transmit Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
3-14
Conexant
100046C
3.4 Transmit Control Registers
0x03
TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register)
The TXFEAC_ERRPAT register is located at address 0x03. The eight MSBs control the FEAC channel used for
DS3. Programming of the FEAC channel is discussed in
Section 2.8
.
The eight LSBs of this register insert BIP-8 errors in the transmitted PLCP, G.832, or SONET overhead or
HEC errors in the cell header for end-to-end testing. The error pattern is XOR
ed with the selected field that is
to be errored.
Bit
Field
Size
Name
Description
15
10
6
Transmit FEAC Data
Six bits of serial data.
9
1
Enable FEAC
Transmission
Enables FEAC transmission; message is transmitted 10 times. Interrupt on DL_INT
when done.
8
1
Enable Receive
FEAC Interrupt
Turns on the interrupt for the FEAC receive.
7
0
8
Error Insertion
Pattern
BIP-8 errors for PLCP, G.832, or SONET.
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