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參數(shù)資料
| 型號(hào)： | 28222-13 |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口 |
| 文件頁(yè)數(shù)： | 41/161頁(yè) |
| 文件大?。?/td> | 1832K |
| 代理商： | 28222-13 |
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Five modes are provided for receiver framing operation: DS3, G.751 E3, G.832
E3/E4, STS-1, and STS-3c/STM-1.
In DS3 mode, a
parallel-search framing circuit recovers the subframe and
M-frame alignments in the DS3 signal. Framing is initiated by an out-of-frame
condition as determined by the receiver frame bit-check circuitry. When 3 out of
16 consecutive subframing (F) bits are in error or when 2 out of 3 consecutive
M-frames have M bit errors, an out-of-frame condition is declared.
In G.751 E3 mode, a
serial search for the 10-bit FAS pattern (1111 0100 00) is
conducted. When three consecutive correct patterns are found, the receiver is
declared to be in frame. An out-of-frame condition is declared when four
consecutive incorrect FAS patterns are detected.
In G.804 E3/E4 and STS-1/STS-3c/STM-1 modes, an octet alignment by the
serial-to-parallel conversion circuit is found in conjunction with an octet search
for the SONET A1/A2 framing pattern (which is the same pattern as, but not
related to, the PLCP A1/A2 bytes). When two consecutive good patterns are
found, the receiver is declared to be in frame. An out-of-frame (OOF) condition is
declared when four consecutive incorrect A1/A2 patterns are detected.
In STS-3c/STM-1 mode, an octet alignment by the serial-to-parallel
conversion circuit is found in conjunction with an octet search for the third A1
and the first A2 octets.
In STS-1 Mode, if STS-1 Stuffing Option [bit 15] in CONFIG_1 [0x00] is set,
then columns 30 and 59 in the payload envelope are stuff columns, and these
octets will not be interpreted as ATM cell octets. If this bit is not set, then all 86
columns of the SPE will be interpreted as ATM cell octets.
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.2 Line Framers
100046C
Conexant
2-7
2.2.2.1 High-Speed
PECL Receive Interface
STS-3c, STM-1 and E4 use the high-speed PECL interface. This mode is used in
any case where an external LIU/decoder is used (such as E4 and STS-3c/STM-1
CMI decoding). If the mode is set to E4 or STS-3c/STM-1 in CONFIG_1, then
the inputs are taken from the
“
HS
±
”
versions of the input pins. RXDATI input is
sampled on the falling edge of RXCKI. RXDATI can be sampled on the rising
edge of the input clock by setting the Invert RX Clock Sampling bit.
Table 2-5
lists the connections for internal framer Rx with the encoder disabled;
Figure 2-6
illustrates the timing with the coder disabled.
2.2.2.2 Receiver
Framing Operation
Table 2-5. Connections for Internal Framer Rx, Encoder Disabled (STS-3c, STM-1, E4)
Signal Name
Connect to CN8223 Pin
Receive Clock Input (RXCKI)
RXCKI or RXCKI_HS±
Receive Data (RXDATI)
RXIN[0] or RXIN_HS±
Receive Loss of Signal (RXLOS~)
RXIN[4]
Figure 2-6. Timing for Internal Framer Receiver, Encoder Disabled
RXCKI
RXDATI
8
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