- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370034 > 28222-13 (Conexant Systems, Inc.) ATM Transmitter/Receiver with UTOPIA Interface PDF資料下載
參數(shù)資料
| 型號(hào)： | 28222-13 |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口 |
| 文件頁數(shù)： | 79/161頁 |
| 文件大小： | 1832K |
| 代理商： | 28222-13 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁
DS3 Terminal Data Link C bits
G.751 E3 N bit
G.832 E3 and E4 GC octet
STS-1/STS-3c/STM-1 D1, D2, D3 octet data link
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.8 FEAC Channel and HDLC Data Link Programming
100046C
Conexant
2-45
2.8.2 FEAC Channel Receiver
The FEAC channel receiver is under control only of the received data stream. The
receiver interrupt is under control of Enable Receive FEAC Interrupt [bit 8] in
TXFEAC_ERRPAT. This interrupt must be enabled by setting this bit for receiver
interrupts to appear on the DL_INT output and for proper interaction with the
processor. The last C bit in subframe 1 in C bit parity mode is provided to the
receiver circuitry at all times.
Receiver status is monitored via Receive FEAC Interrupt [bit 9] in
RXFEAC_VER. When a receive FEAC channel interrupt is generated on
DL_INT, the Receive FEAC Interrupt bit will be set in 0x3C. If this bit is
observed upon reading the RXFEAC_VER, then at least 10 repetitions of the
same byte have been received by the data link and placed in bits 15
–
10 of
RXFEAC_VER. The receive interrupt serves as notice that the message bits in
RXFEAC_VER are valid. Reading RXFEAC_VER clears the receive interrupt.
An idle message is all 1s, and all other messages are of the form
“
0xxxmmm011111111
”
with reception of the rightmost bit first from the
channel. The receiver logic recognizes the eight 1s message flag followed by a
message byte and interrupts the controller upon reception of 10 repetitions of a
valid message byte. The
“
mmmxxx
”
message byte that was received is stored in
RXFEAC_VER bits 15
–
10 at 0x3C. Continuous incoming messages on the
FEAC channel produce an interrupt rate of approximately one interrupt per 17 ms
for this interrupt source. No interrupts are generated if the FEAC channel is
receiving continuous idle flags or if the interrupt is not enabled in
TXFEAC_ERRPAT.
2.8.3 HDLC Data Link Transmitter
The HDLC data link capability is present in the following formats:
The HDLC formatter has an 8-octet buffer (organized as four 16-bit words)
for both the receiver and transmitter, located at addresses 0x58 through 0x5B and
0x5C through 0x5F, respectively. Addresses are word-wide locations that hold 2
bytes each. Therefore, each buffer has an address range of 4, two for each buffer
half. Each buffer holds 4 octets.
The HDLC data link transmitter is under the control of the Enable HDLC Data
Link [bit 5] in the CONFIG_5 [0x31] and bits 6
–
0 in DL_CTRL_STAT [0x60].
An interrupt for use with data link operations is available on the DL_INT output
pin, and status bits for determining the interrupt source are located in
DL_CTRL_STAT.
If the framer is in a mode that allows data link transmission as described
above, the DL_CTRL_STAT register is the main control register used for transmit
data link operations. Disable Data Link Transmission [bit 6] of DL_CTRL_STAT
must be set low to enable operation of the data link. If this bit is set high, an all 1s
signal is transmitted in the data link bit positions in the outgoing serial stream.
With the data link enabled, the Send Message [bit 0], Send FCS [bit 1], and Abort
Message [bit 2] bits of DL_CTRL_STAT control operation. TxBytes[2:0] [bits
5
–
3] of DL_CTRL_STAT form a pointer to the TX_DL_BUFFER used by the
data link transmitter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28222-14 | ATM Transmitter/Receiver with UTOPIA Interface |
| 28233-11 | ATM Transmitter/Receiver with UTOPIA Interface |
| 28C010TRPDB-12 | 150 x 32 pixel format, LED Backlight available |
| 28C010TRT1DE-15 | 1 Megabit (128K x 8-Bit) EEPROM |
| 28C010TRT1DE-20 | 1 Megabit (128K x 8-Bit) EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28222-14 | 制造商:CONEXANT 制造商全稱:CONEXANT 功能描述:ATM Transmitter/Receiver with UTOPIA Interface |
| 282222-003 | 制造商:TE Connectivity 功能描述:81044/12-16-2 - Cable Rools/Shrink Tubing |
| 282223-003 | 制造商:TE Connectivity 功能描述:81044/12-16-3 - Cable Rools/Shrink Tubing |
| 282224-003 | 制造商:TE Connectivity 功能描述:81044/12-16-4 - Cable Rools/Shrink Tubing |
| 282224-1 | 功能描述:汽車連接器 ECONOSEAL RCPT CONT .5MM RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點(diǎn)電鍍:Nickel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。