CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.6 Interrupt Enable Control Registers
100046C
Conexant
3-27
0x30
—
EN_CELL_INT (Enable Cell Interrupts)
The EN_CELL_INT register (0x30) enables interrupts for the CELL_STATUS register (0x3B). Setting a bit in
EN_CELL_INT enables each interrupt condition to appear on STAT_INT (pin 64).
0x32
—
TX_K1K2 (Transmit K1 and K2 Value)
The TX_K1K2 register (0x32) contains the APS Transmit K1 and K2 values.
0x33
—
RX_K1K2 (Receive K1 and K2 value)
The RS_K1K2 register (0x33) contains the APS Receive K1 and K2 values.
Bit
Field
Size
Name
Description
15
1
Cell Sent Cntr Ovfl
–
Port 3
Enables an interrupt if the CELL_SENT_CNT3 counter overflows.
14
1
Cell Sent Cntr Ovfl
–
Port 2
Enables an interrupt if the CELL_SENT_CNT2 counter overflows.
13
1
Cell Sent Cntr Ovfl
–
Port 1
Enables an interrupt if the CELL_SENT_CNT1 counter overflows.
12
1
Cell Sent Cntr Ovfl
–
Port 0
Enables an interrupt if the CELL_SENT_CNT0 counter overflows.
11
1
Cell Rcvd Cntr Ovfl-Port 3
Enables an interrupt if the CELL_RCV_CNT3 counter overflows.
10
1
Cell Rcvd Cntr Ovfl-Port 2
Enables an interrupt if the CELL_RCV_CNT2 counter overflows.
9
1
Cell Rcvd Cntr Ovfl-Port 1
Enable an interrupt if the CELL_RCV_CNT1 counter overflows.
8
1
Cell Rcvd Cntr Ovfl-Port 0
Enables an interrupt if the CELL_RCV_CNT0 counter overflows.
7
1
Cell Rcvd
–
Port 3
Enables port 3 header match interrupt.
6
1
Cell Rcvd
–
Port 2
Enables port 2 header match interrupt.
5
1
Cell Rcvd
–
Port 1
Enables port 1 header match interrupt.
4
1
Cell Rcvd
–
Port 0
Enables port 0 header match interrupt.
3
1
Cell Sent
–
Port 3
Enables an interrupt when a cell is transmitted from port 3.
2
1
Cell Sent
–
Port 2
Enables an interrupt when a cell is transmitted from port 2.
1
1
Cell Sent
–
Port 1
Enables an interrupt when a cell is transmitted from port 1.
0
1
Cell Sent
–
Port 0
Enables an interrupt when a cell is transmitted from port 0.
Bit
Field
Size
Name
Description
15-8
8
TX_K1
Value to transmit in the K1 byte of the SONET frame.
7-0
8
TX_K2
Value to transmit in the K2 byte of the SONET frame.
Bit
Field
Size
Name
Description
15-8
8
RX_K1
Value of the last K1 byte received in the SONET frame. A change in this value causes
Bit 12 of the EVENT_STATUS register to be set.
7-0
8
RX_K2
Value of the last K2 byte received in the SONET frame. A change in this value causes
Bit 12 of the EVENT_STATUS register to be set.