- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄206198 > XQV300-4BGG352N (XILINX INC) FPGA, 1536 CLBS, 322970 GATES, PBGA352 PDF資料下載
參數(shù)資料
| 型號： | XQV300-4BGG352N |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 322970 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 253K |
| 代理商： | XQV300-4BGG352N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
QPro Virtex 2.5V QML High-Reliability FPGAs
16
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605; all devices are 100 per-
cent functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions.
Symbol
Description
Speed Grade -4
Units
Min
Max
FCLKINHF
Input clock frequency (CLKDLLHF)
60
180
MHz
FCLKINLF
Inputclock frequency (CLKDLL)
25
90
MHz
TDLLPWHF
Input clock pulse width (CLKDLLHF)
2.4
-
ns
TDLLPWLF
Input clock pulse width (CLKDLL)
3.0
-
ns
Notes:
1.
All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Symbol
Description
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
TIPTOL
Input clock period tolerance
-
1.0
-
1.0
ns
TIJITCC
Input clock jitter cycle to cycle
-
±150
-
±300
ps
TLOCK
Time required for DLL to acquire Lock
FCLKIN
> 60 MHz
-
20
-
20
s
50-60 MHz
-
25
s
40-50 MHz
-
50
s
30-40 MHz
-
90
s
25-30 MHz
-
120
s
TSKEW
DLL output skew (between any DLL output)
-
±150
-
±150
ps
TOPHASE
DLL output long term phase differential
-
±100
-
±100
ps
TOJITCC
DLL output ditter cycle to cycle
-
±60
-
±60
ps
Notes:
1.
All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Figure 1: Frequency Tolerance and Clock Jitter
TCLKIN
TCLKIN + TIPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Clock Jitter: the difference between an ideal reference clock edgfe and the actual design.
TOJITCC
+
_
DS002_01_060100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17D154CV | UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART |
| XR17D154IV | UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART |
| XR17D154 | UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART |
| XRD8785 | CMOS 8-Bit High Speed Analog-to-Digital Converter |
| XRT7250IQ100 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQV600 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Military 4Mbit ISP Configuration Flash PROM |
| XQVR1000 | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs |
| XQVR1000-4CG560M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs |
| XQVR1000-4CG560V | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs |
| XQVR300 | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。