參數(shù)資料
型號(hào)： XQV300-4BGG352N
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： FPGA, 1536 CLBS, 322970 GATES, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 31/31頁(yè)
文件大?。?/td> 253K
代理商： XQV300-4BGG352N
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
R
Calculation of Tioop as a Function of Capacitance
The values for Tioop were based on the standard capacitive
load (Csl) for each I/O standard as listed in Table 2.
For other capacitive loads, use the formulas below to calcu-
late the corresponding Tioop:
Tioop = Tioopl + Topadjust + (Cload - Csl) * fl
Where:
Topadjust is reported above in the Output Delay
Adjustment section.
Cload is the capacitive load for the design.
Clock Distribution Guidelines and Switching Characteristics
Table 2: Constants for Use in Calculation of Top
Standard
Csl (pF)
fl (ns/pF)
LVTTL slow
slew rate
2 mA drive
35
0.41
4 mA drive
35
0.20
6 mA drive
35
0.100
8 mA drive
35
0.086
12 mA drive
35
0.058
16 mA drive
35
0.050
24 mA drive
35
0.048
LVTTL fast
slew rate
2 mA drive
35
0.41
4 mA drive
35
0.20
6 mA drive
35
0.13
8 mA drive
35
0.079
12 mA drive
35
0.044
16 mA drive
35
0.043
24 mA drive
35
0.033
LVCMOS2
35
0.041
PCI 33 MHz 5V
50
0.050
PCI 33 MHZ 3.3V
10
0.050
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class 1
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Table 2: Constants for Use in Calculation of Top
Standard
Csl (pF)
fl (ns/pF)
Symbol
Description
Device
Speed Grade
Units
-4
Min
Max
Global Clock Skew
TGSKEWIOB
Global clock skew between IOB flip-flops
XQV100
-
0.15
ns
XQV300
-
0.18
ns
XQV600
-
0.17
ns
XQV1000
-
0.25
ns
TGPIO
Global clock PAD to output
All
-
0.9
ns
TGIO
Global clock buffer I input to O output
All
-
0.9
ns
Notes:
1.
These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
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