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參數(shù)資料
| 型號(hào)： | XQV300-4BGG352N |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 322970 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 253K |
| 代理商： | XQV300-4BGG352N |
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QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
13
Preliminary Product Specification
1-800-255-7778
R
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Virtex Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Listed below are representative
values for typical pin locations and normal clock loading.
Values are expressed in nanoseconds unless otherwise
noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Symbol
Description
Speed Grade
Units
-4
Min
Max
Combinatorial Delays
TIO
IN input to OUT output
-
0.0
ns
TOFF
TRI input to OUT output high-impedance
-
0.2
ns
TON
Tri input to valid data on OUT output
-
0.2
ns
Symbol
Description
Speed Grade
Units
-4
Min
Max
TTAPTCK
TMS and TDI setup times before TCK
4.0
-
ns
TTCKTAP
TMS and TDI hold times after TCK
2.0
-
ns
TTCKTDO
Output delay from clock TCK to output TDO
-
11.0
ns
FTCK
Maximum TCK clock frequency
-
33
MHz
Symbol
Description
Device
Speed Grade
Units
-4
Min
Max
LVTTL Global Clock Input to Output Delay using Output Flip-flop,
12 mA, Fast Slew Rate, with DLL. For data output with different
standards, adjust the delays with the values shown in "IOB Output
XQV100
-
3.6
ns
XQV300
-
3.6
ns
XQV600
-
3.6
ns
XQV1000
-
3.6
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2.
3.
DLL output jitter is already included in the timing calculation.
Symbol
Description
Device
Speed Grade
Units
-4
Min
Max
LVTTL Global Clock Input to Output Delay using Output Flip-flop,
12 mA, Fast Slew Rate, without DLL. For data output with different
standards, adjust the delays with the values shown in "IOB Output
XQV100
-
5.7
ns
XQV300
-
5.9
ns
XQV600
-
6.0
ns
XQV1000
-
6.3
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2.
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