參數(shù)資料
型號(hào): XQV300-4BGG352N
廠商: XILINX INC
元件分類: FPGA
英文描述: FPGA, 1536 CLBS, 322970 GATES, PBGA352
封裝: PLASTIC, BGA-352
文件頁數(shù): 3/31頁
文件大?。?/td> 253K
代理商: XQV300-4BGG352N
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Symbol
Description
Speed Grade
Units
-4
Min
Max
Combinatorial Delays
TOPX
F operand inputs to X via XOR
-
1.0
ns
TOPXB
F operand input to XB output
-
1.4
ns
TOPY
F operand input to Y via XOR
-
2.0
ns
TOPYB
F operand input to YB output
-
2.0
ns
TOPCYF
F operand input to COUT output
-
1.5
ns
TOPGY
G operand inputs to Y via XOR
-
1.2
ns
TOPGYB
G operand input to YB output
-
2.1
ns
TOPCYG
G operand input to COUT output
-
1.6
ns
TBXCY
BX initialization input to COUT
-
1.1
ns
TCINX
CIN input to X output via XOR
-
0.6
ns
TCINXB
CIN input to XB
-
0.1
ns
TCINY
CIN input to Y via XOR
-
0.6
ns
TCINYB
CIN input to YB
-
0.6
ns
TBYP
CIN input to COUT output
-
0.2
ns
Multiplier Operation
TFANDXB
F1/2 operand inputs to XB output via AND
-
0.5
ns
TFANDYB
F1/2 operand inputs to YB output via AND
-
1.1
ns
TFANDCY
F1/2 operand inputs to COUT output via AND
-
0.6
ns
TGANDYB
G1/2 operand inputs to YB output via AND
-
0.7
ns
TGANDCY
G1/2 operand inputs to COUT output via AND
-
0.2
ns
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
TCCKX/TCKCX
CIN input to FFX
1.3 / 0
-
ns
TCCKY/TCKCY
CIN input to FFY
1.4 / 0
-
ns
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if
a “0” is listed, there is no positive hold time.
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