參數(shù)資料
型號(hào)： XQV300-4BGG352N
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： FPGA, 1536 CLBS, 322970 GATES, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 10/31頁(yè)
文件大?。?/td> 253K
代理商： XQV300-4BGG352N
QPro Virtex 2.5V QML High-Reliability FPGAs
18
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
VREF, Bank 0
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 229
XQV300
... + 236
XQV600
... + 230
VREF, Bank 1
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 194
XQV300
... + 187
XQV600
... + 193
VREF, Bank 2
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 168
XQV300
... + 175
XQV600
... + 169
VREF, Bank 3
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 133
XQV300
... + 126
XQV600
... + 132
VREF, Bank 4
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 108
XQV300
... + 115
XQV600
... + 109
VREF, Bank 5
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 73
XQV300
... + 66
XQV600
... + 72
VREF, Bank 6
(VREF pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all VREF
pins are general I/O.
XQV100
... + 47
XQV300
... + 54
XQV600
... + 48
Table 3: Virtex QFP Package Pinout Information (Continued)
Pin Name
Device
PQ/HQ240
相關(guān)PDF資料
PDF描述
XR17D154CV UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
XR17D154IV UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
XRD8785 CMOS 8-Bit High Speed Analog-to-Digital Converter
XRT7250IQ100 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XQV600 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Military 4Mbit ISP Configuration Flash PROM
XQVR1000 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs
XQVR1000-4CG560M 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs
XQVR1000-4CG560V 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs
XQVR300 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Virtex 2.5V Radiation Hardened FPGAs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*