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參數(shù)資料
| 型號： | XQV300-4BGG352N |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 322970 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 253K |
| 代理商： | XQV300-4BGG352N |
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QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
15
Preliminary Product Specification
1-800-255-7778
R
Virtex Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Listed below are representative
values for typical pin locations and normal clock loading.
Values are expressed in nanoseconds unless otherwise
noted
Global Clock Setup and Hold for LVTTL Standard, with DLL
Global Clock Setup and Hold for LVTTL Standard, without DLL
Symbol
Description
Device
Speed Grade
Units
-4
Min
Max
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
TPSDLL/TPHDLL
No Delay
Global clock and IFF, with DLL
XQV100
2.1 / –0.4
-
ns
XQV300
2.1 / –0.4
-
ns
XQV600
2.1 / –0.4
-
ns
XQV1000
2.1 / –0.4
-
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
Symbol
Description
Device
Speed Grade
Units
-4
Min
Max
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
TPSFD/TPHFD
Full Delay
Global clock and IFF, without DLL
XQV100
3.0 / 0.0
-
ns
XQV300
3.1 / 0.0
-
ns
XQV600
3.3 / 0.0
-
ns
XQV1000
3.6 / 0.0
-
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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