參數(shù)資料
型號(hào)： XQV300-4BGG352N
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 1536 CLBS, 322970 GATES, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 23/31頁(yè)
文件大?。?/td> 253K
代理商： XQV300-4BGG352N
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
3
Preliminary Product Specification
1-800-255-7778
R
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Max
Units
VCCINT
Supply voltage relative to GND, TC = –55°C to +125°C Ceramic packages
2.5 – 5%
2.5 + 5%
V
Supply voltage relative to GND, TJ = –55°C to +125°C Plastic packages
2.5 – 5%
2.5 + 5%
V
VCCO
Supply voltage relative to GND, TC = –55°C to +125°C Ceramic packages
1.2
3.6
V
Supply voltage relative to GND, TJ = –55°C to +125°C Plastic packages
1.2
3.6
V
TIN
Input signal transition time
-
250
ns
TIC
Initialization Temperature Range(4)
XQVR300
–55
+125
°C
XQVR600
–55
+125
°C
XQVR1000
–40
+125
°C
TOC
Operational Temperature Range(5)
XQVR300
–55
+125
°C
XQVR600
–55
+125
°C
XQVR1000
–55
+125
°C
Notes:
1.
Correct operation is guaranteed with a minimum VCCINT of 2.25V (Nominal VCCINT – 10%). Below the minimum value stated above,
all delay parameters increase by 3% for each 50 mV reduction in VCCINT below the specified range.
2.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°C.
3.
Input and output measurement threshold is ~50% of VCC.
4.
Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin.
5.
The device is operational after the INIT pin has transitioned high.
Symbol
Description
Device
Min
Max
Units
VDRINT
Data retention VCCINT voltage
(below which configuration data may be lost)
All
2.0
-
V
VDRIO
Data retention VCCO voltage
(below which configuration data may be lost)
All
1.2
-
V
ICCINTQ
Quiescent VCCINT supply current(1)
XQV100
-
50
mA
XQV300
-
75
mA
XQV600
-
100
mA
XQV1000
-
100
mA
ICCOQ
Quiescent VCCINT supply current(1)
XQV100
-
2
mA
XQV300
-
2
mA
XQV600
-
2
mA
XQV1000
-
2
mA
IREF
VREF current per VREF pin
-
20
A
IL
Input or output leakage current
-
–10
+10
A
CIN
Input capacitance (sample tested)
-
8
pF
IRPU
Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V (sample tested)
-
(2)
0.25
mA
IRPD
Pad pull-down (when selected) at VIN = 3.6V (sample tested)
-
(2)
0.15
mA
Notes:
1.
With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.
2.
Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
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