參數(shù)資料
型號: TSB42AB4PGE
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費電子產(chǎn)品鏈路層控制器
文件頁數(shù): 69/183頁
文件大小: 798K
代理商: TSB42AB4PGE
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁當前第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁
54
Table 54. Block Transmit Format Functions
FIELD NAME
DESCRIPTION
spd
The spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mb/s,
01 = 200 Mb/s, and 10 = 400 Mb/s. For this implementation, 11 is undefined.
tLabel
The tLabel field is the transaction label, which is a unique tag for each outstanding
transaction between two nodes. This field is used to pair up a response packet with its
corresponding request packet.
rt
The rt field is the retry code for the current packet is 00 = new, 01 = retry_X, 10 = retry_A, and
11 = retry_B.
tCode
tCode is the transaction code for the current packet (see Table 610 of IEEE-1394 standard).
priority
The priority level for the current packet. For cable implementation, the value of the bits must
be zero. For backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE-1394
standard.
destinationID
The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node
number that forms the node address to which the current packet is being sent.
destination OffsetHigh,
destination OffsetLow
The concatenation of the destination OffsetHigh and the destination OffsetLow fields
addresses a quadlet in the destination node address space. This address must be quadlet
aligned (modulo 4). The upper 4 bits of the destination OffsetHigh field are used as the
response code for lock-response packets and the remaining bits are reserved.
dataLength
The dataLength field contains the number of bytes of data to be transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in the current packet (see Table 611
of the IEEE-1394 standard)
block data
The block data field contains the data to be sent. If dataLength is 0, no data should be written
into the FIFO for this field. Regardless of the destination or source alignment of the data, the
first byte of the block must appear in byte 0 of the first quadlet.
5.2
Asynchronous Receive
There are two basic formats for received asynchronous data. The first is for quadlet packets, and the second
is for block packets. The asynchronous receive data buffer can be accessed by either the HSDI or the MCIF.
The data buffers can be accessed by the MCIF through the DB(N)ACC0 register.
The full received packet format with headers and data is shown in Figure 55 and Figure 56. ceLynx can
strip received packet headers on a quadlet basis. This is controlled in the RXDPB(N)CFG0 register bits 03.
For example, the application can choose to strip quadlet headers 0, 1, and 2. The application receives
header 3 and the data. In this example, if ceLynx received an asynchronous block read response packet,
the application receives the dataLength and extended t-code quadlet and the packet data only.
The packet control token gives information about the received packet. For asynchronous packets, the
quadlet is included with the data in the data buffer according to the RXDPB(N)CFG0.INSERTPKT
TOKEN bit. The control token is always attached to receive self-ID packets regardless of the
RXDPB(N)CFG0.INSERTPKTTOKEN setting. The packet control token format for asynchronous and PHY
packets is shown in Figure 55 and Table 55.
30
29
16
15
14
13
12
8
7
6
5
4
3
0
31
rsv
pad
ACK
P
S
SIZE
spd
rsv
rsv
Figure 55. Packet Control Token Format for Asynchronous,
Self-ID, and PHY Packets
相關(guān)PDF資料
PDF描述
TSB43AA82A1 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
TSB81BA3I IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSE-0155-32S-P1-3 SINGLE MODE SINGLE FIBER TRANSCEIVER
TSL230 PROGRAMMABLE LIGHT-TO-FREQUENCY CONVERTERS
TSL235(中文) Programmable Light-To-Frequency Converter(光頻轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB42AC3 制造商:TI 制造商全稱:Texas Instruments 功能描述:General purpose link layer ideal for a wide-range of applications
TSB42AC3IPZT 制造商:TI 制造商全稱:Texas Instruments 功能描述:General purpose link layer ideal for a wide-range of applications
TSB42AC3PZT 功能描述:1394 接口集成電路 High Perf 1394-1995 Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB42AC3PZTG4 功能描述:1394 接口集成電路 High Perf 1394-1995 Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB432 制造商:Ssac 功能描述: