參數(shù)資料
型號(hào)： TSB42AB4PGE
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述： 1394消費(fèi)電子產(chǎn)品鏈路層控制器
文件頁(yè)數(shù)： 56/183頁(yè)
文件大?。?/td> 798K
代理商： TSB42AB4PGE
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44
An offset, programmed in ceLynx CFRs, can be added to the receiver time stamp. The time stamp plus the
the offset value determines when a packet is aged in the buffer. A packet is aged when the receive time
stamp plus offset value is less than the current cycle time. At this point, the packet is flushed from the buffer.
If receive aging is used, a receive offset must be added.
See Figure 43 for an explanation of packet again.
Release Time
Aged Time
Receive Offset
Time Stamp = Cycle Timer
Application Can Read
Data From Buffer
Time Stamp +Receive Offset = Cycle Timer
Packet is Flushed if it Has Not Been Read
Out of Buffer
Figure 43. MPEG2 Receive, Release, and Aging
4.2.1.1
MPEG2 Time Stamp Calculation on Transmit
The transmit time stamp is computed by adding an offset value to the current cycle timer value. The offset
is programmed in DB(N)CFG2 register. The determination of the transmit time stamp is shown in Figure 44.
12
24
Cycle Timer
0
11
Time Stamp Offset Value
DB(N)CFG2 Register
Transmit
Time Stamp
+
Cycle Offset
Cycle Count
Figure 44. Determination of Transmit Time Stamp
The time stamp values are limited by the restraints of the 125
μ
s 1394 isochronous cycle. The cycle timer
operates using the internal 24.576-MHz clock. When the cycle offset reaches
3071
, 125
μ
s have elapsed.
(3071/24.576 MHz = 125
μ
s) It is necessary to limit the cycle offset value to equal or less than 3071 to avoid
creating an invalid time stamp. When the cycle offset reaches 3071, it rolls over to zero and starts again.
If the sum of the cycle timer value and the transmit offset results in cycle offset greater than 3071, the cycle
count field is incremented by one and the new cycle offset is (cycle offset – 3072.)
The cycle count operates at a frequency of 8 kHz. (1/125
μ
s = 8 kHz). One second has elapsed every time
the cycle count reached 8000. The cycle count rolls over after it reaches 7999. If the sum of the cycle timer
value and the transmit offset results in cycle count greater than 7999, the seconds count field is incremented
by one and the new cycle count is (cycle count – 8000.)
Table 42 shows the allowable values of the transmit time stamp.
Table 42. Allowable Values for 1394 Time Stamps
BIT NUMBER
VALUE
VALID RANGE
24:12
Cycle Count
Between 0 and 7999
11:0
Cycle Offset
Between 0 and 3071
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TSB432 制造商:Ssac 功能描述:
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