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| 型號(hào)： | TSB42AB4PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁(yè)數(shù)： | 27/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AB4PGE |
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32
timing. If the host asserts this signal, the ceLynx asserts the MCIF_ACK pin when
either the data on MCIF_D[15:0] is valid (during a read access) or the data on
MCIF_D[15:0] has been latched (during a write access). As soon as the host
deasserts this signal, the ceLynx deasserts the MCIF_ACK.
Status of the MCIF_CS pin. When this signal is asserted, the MCIF_ACK assumes that
ceLynx is the only peripheral device currently selected on the MCIF interface, and as such,
it drives the MCIF_ACK pin either asserted or deasserted.
Setting of the PINCFG.MCACKZFLT bit at 0x004. When this register bit is set
to 0, the MCIF_ACK signal is always in the high-impedance state and the ceLynx
never asserts the MCIF_ACK pin. The ceLynx never asserts the MCIF_ACK pin.
The user must never set this bit to 0, because this prevents communication with
the host. If this register bit is set to 1 (default), then the MCIF_ACK pin output drivers
are turned off when the pin is deasserted (assuming the MCIF_CS pin is
deasserted).
Setting of MCIFCFG.MCACKZDLY bits at 0x010. These bits work in conjunction
with the MCACKZFLT mode to control the time that the MCIF_ACK pin is
deasserted before the pin output drivers, described previously, are turned off. This
delay can be adjusted from 0 ns (default) up to 10 ns. If the MCACKZFLT register
bit is set to 0, the MCACKZDLY register bits are ignored.
Figure 31 shows the typical connection between ceLynx and a 68000-style processor.
ceLynx
68000-Style
MCIF_D15 (MSB)
MCIF_D[14:0]
MCIF_A[9:2]
MCIF_A1
MCIF_S32
MCIF_STRB
MCIF_CS
MCIF_RW
MCIF_ACK
INT
D15 (MSB)
D[14:0]
Address Bus
Address (LSB+1)
Address LSB
CS
RW
DTACK
INT
NC
3.3 V
NOTES:
1. MCIF_S32 is used for controllers that can supply a single address for a 32-bit transaction.
2. MCIF_STRB is provided for controllers that have separate strobe and chip select signals. The MCIF_STRB
and MCIF_CS signals can be tied together if the application processor does not have a separate strobe
signal.
Figure 31. Interface Between ceLynx and 68000-Style Processor
Read Operation
3.1.1
Figure 32 depicts a typical read operation using 16-bit transactions. The host begins the read access by
driving the address to be read from onto MCIF_A[9:1]. The host then drives MCIF_RW high to indicate a
read. The host drives MCIF_STRB low to indicate that it is ready to receive the data. MCIF_CS selects the
link as the peripheral being accessed. Note the MCIF_STRB signal acts as a master enable on the
microcontroller interface. No transactions occur unless MCIF_STRB is active. The address is sampled on
the falling edge of MCIF_CS and begins the internal read access to the specified CFR. After the 16-bit word
is retrieved from the internal CFR, the link responds by driving the data onto the data bus and driving
MCIF_ACK low to indicate that data is available
The difference in functionality of a 32-bit read transaction is that the host indicates a 32-bit access by driving
MCIF_S32 active low. The host only gives one address for the entire transaction. In this mode, the MCIF
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