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| 型號(hào)： | TSB42AB4PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁(yè)數(shù)： | 41/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AB4PGE |
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316
In sync mode C, Figure 317, the HSDIx_SYNC signal is used to indicate the last byte of data. In this
example, the last byte of the first packet is 1E. The last byte of the second packet is 56. Data is valid on the
bus as soon as HSDIx_EN is active. Data does not change until the HSDIx_EN signal is active.
HSDIx_CLK
HSDIx_SYNC
HSDIx_RW
HSDIx_AV
HSDIx_EN
HSDIx_A[2:0]
HSDIx_D[0]
XX
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
000h
First Bit
Figure 318. HSDI Read, Serial Data Bus, Sync Mode B
Figure 318 shows serial mode functional timing for sync mode B. Sync modes A and C would have similar
timing. For sync mode A, no HSDIx_SYNC signal is used. For sync mode B, the HSDIx_SYNC signal
indicates the first byte of the packet. For sync mode C, the HSDIx_SYNC signal indicates the last byte of
the packet. The function of the HSDIx_SYNC signal is programmable in CFR. In Figure 318, the
HSDIx_SYNC signal is driven for one bit. It can also be asserted for an entire byte.
The HSDIx_EN and HSDIx_AV signals function the same as byte mode. HSDIx_EN must be asserted and
deasserted on quadlet boundaries, except in DirecTV 130 byte mode.
The bit ordering can be programmed. The default state is to read the most significant bit first.
This mode has been verified in design simulation only.
3.2.4
HSDI Functional Timing Write
HSDIx_CLK
HSDIx_SYNC
HSDIx_RW
HSDIx_AV
HSDIx_EN
HSDIx_A[2:0]
HSDIx_D[7:0]
X
XX
00
A9
1E
XX
03
FF
47
3F
76
56
XX
Figure 319. HSDI Write, Byte-Wide Data Bus, Sync Mode A
In sync mode A write, Figure 319, the HSDIx_SYNC signal is ignored by the HSDI. An internal counter
keeps track of packet boundaries. The HSDIx_EN signal should only be asserted for valid data on the bus.
Otherwise, invalid data is written into the FIFO.
XX
HSDIx_CLK
HSDIx_SYNC
HSDIx_RW
HSDIx_AV
HSDIx_EN
HSDIx_A[2:0]
HSDIx_D[7:0]
X
XX
76
A9
03
23
FF
47
3F
76
XX
Figure 320. HSDI Write, Byte-Wide Data Bus, Sync Mode B
In sync mode B write, Figure 320, the HSDIx_SYNC signal indicates the start of the next packet. In this
example, the first packet is 76 A9 03 23. The second packet is FF 47 3F 76. All packets must be at least
4 bytes long. The HSDIx_SYNC signals are ignored if HSDIx_EN is not active.
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