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參數(shù)資料
| 型號： | TSB42AA4PDT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費電子產(chǎn)品鏈路層控制器 |
| 文件頁數(shù)： | 57/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA4PDT |
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45
4.2.1.2
MPEG2 Time Stamp Calculation on Receive
Receiving packets with time stamps works similarly to the transmit process. When a packet with a time
stamp is received, the time stamp is captured and compared to the current cycle timer value. The time stamp
determines when ceLynx releases the packet data to the application.
If receive aging is enabled, the received packet is flushed from the FIFO if its time stamp value has expired.
The time stamp used for aging, is the received time stamp plus a time stamp offset.
4.2.2
Time Stamp on Transmit to 1394 DV Data
DV_Frame_In
DV Frame 1
DV Frame 2
Time Stamp Value Is Calculated
Time Stamp Is Placed
At Next Start Of Frame
Figure 45. DV Transmit Timing
In Figure 45 the DV_Frame_In (programmable at GPIO) is used to create the time stamp for a DV packet.
The signal should be 29.97 Hz for NTSC and 25 Hz for PAL, 50% duty cycle. The cycle timer is recorded
at the time the DV_frame_In signal goes active. The value of the time stamp defined in IEC61883-2 is
determined from the recorded value of the cycle timer register and transmit offset. The time stamp is then
added to the next start of frame packet transmitted.
The DV_frame_In signal should be close to the start of a new frame or the transmit offset must be large
enough to compensate for the delay.
The time stamp is calculated by adding an offset to the value of the cycle timer register. This offset is
programmed in DB(N) CFG2 register. The 16 bit time stamp value is placed in the SYT field of the CIP
header. The least significant 12 bits after the addition of cycle timer register and DB(N) CFG register is
lowadd
. The four most significant bits after the addition is
highadd
.
The time stamp can be placed in the first data packet of the frame (empty or full) or in the first full data packet
of the frame. This is controlled by the TXDP(N) CFG register.
The cycle timer register is made up of the cycle count (4 most significant bits) and the cycle offset (12 least
significant bits). The cycle-offset portion of the cycle timer register is modulo 3072. Each time this counter
wraps around it signals the beginning of a new isochronous cycle. For a cycle master device, a cycle start
packet is transmitted at the beginning of each new isochronous cycle. For a non-cycle master device a cycle
start is decoded from a received cycle start packet.
Highadd specifies the offset in number of isochronous cycles, and lowadd specifies an offset into an
isochronous cycle. If the computation results in a lowadd which is less than 3072 (125
μ
s) then the resultant
time stamp is simply highadd and lowadd. If the computation results in a lowadd which is equal to or greater
than 3072 then the resultant time stamp is highadd + 1 and the difference between the computed lowadd
and 3072.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AA4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA9I | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AA9IPZT | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AA4PDTR | 制造商:Texas Instruments 功能描述: |
| TSB42AA4PGE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PGER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
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