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636
0x0E8 INSBUFB_CSR0 – Insertion Buffer B Configuration and Status 0
BIT
NAME
TYPE
RESET
FUNCTION
31
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
30
WRPTR_RST
R0WU
0
Insertion buffer write pointer reset – When the packet insertion
feature is disabled, writing a 1 to this location causes the insertion
buffer write pointer to be set to 0. When the packet insertion feature is
enabled, access to this bit has no effect. This bit is self-clearing.
29:24
WRPTR
RU
0
Insertion buffer write pointer – This read-only value indicates the next
location that is updated by a write access to INSBUFB_ACC. When
the packet insertion feature is disabled, writes to INSBUFB_ACC
cause this field to increment.
23
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
22
RDPTR_RST
R0WU
0
Insertion buffer read pointer reset – When the packet insertion
feature is disabled, writing a 1 to this location causes the insertion
buffer read pointer to be set to 0. When the packet insertion feature is
enabled, access to this bit has no effect. This bit is self-clearing.
21:16
RDPTR
RU
0
Insertion buffer read pointer – This read-only value indicates the next
location that is returned by a read access to INSBUFB_ACC. When
the packet insertion feature is enabled, this field reflects the current
insertion buffer location being accessed by hardware.
15:11
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
10:8
INSRT_BUF
RW
0
Insertion buffer mapping – When the packet insertion feature is used,
this field must be written by software to indicate which of the eight
highly configurable data buffers to place the insertion packet in.
7
AUTOFILL
R0W
0
Auto fill – Writing a 1 in this location causes all locations in the
insertion buffer starting from the address indicated by
INSBUFB_CSR0.WRPTR to be filled with 0xFFFF FFFF.
6
PKTINSRT_EN
RWU
0
Packet insertion enable – Writing a 1 to this location enables the
packet insertion feature. All packet insertion related configurations
must be complete prior to setting this bit. This bit is cleared by
hardware in the event of a successful packet insertion event. Setting
this bit causes the insertion buffer read/write pointers to reset to 0.
5:0
PKTSIZE
RW
0
Packet size – Software must update this field with the size of the
inserted packet in quadlets.
0x0EC INSBUFB_CSR1 – Insertion Buffer B Configuration and Status 1
BIT
NAME
TYPE
RESET
FUNCTION
31:16
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
15:0
OFPT
RW
0
Offset packet time – If enabled, the link inserts a packet into the 1394
isochronous stream if a gap exists in the transport stream equal to or
greater than the value of OFPT.
The format is identical to the 1394 cycle timer:
bits 15:12 cycle count
bits 11:0 cycle offset
For a transport stream with HSDIx_CLK of 3 MHz, a gap length to
insert 188 bytes is computed as follows:
188 bytes/3MHz = 62.5
μ
s
cycle count = (0
×
125
μ
s) = 0h
cycle offset = (62.5
μ
s/25 ns) = 9CAh
OFPT = 0000_9CAh