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0x248 TXDPINT – Transmit Data Path Interrupts (Continued)
BIT
NAME
TYPE
RESET
FUNCTION
5
ERRDBC6
RCU
0
Buffer 6 DBC error When this bit is set to 1 by hardware, the TXDP has
detected a data block continuity error in an MPEG/DV packet.
4
ERRDBC7
RCU
0
Buffer 7 DBC error When this bit is set to 1 by hardware, the TXDP has
detected a data block continuity error in an MPEG/DV packet.
3
ERRTH0_4
RCU
0
Buffer 4 transmit header error When this bit is set to 1 by hardware, the
TXDP has detected an error in the transmit packet header.
2
ERRTH0_5
RCU
0
Buffer 5 transmit header error When this bit is set to 1 by hardware, the
TXDP has detected an error in the transmit packet header.
1
ERRTH0_6
RCU
0
Buffer 6 transmit header error When this bit is set to 1 by hardware, the
TXDP has detected an error in the transmit packet header.
0
ERRTH0_7
RCU
0
Buffer 7 transmit header error When this bit is set to 1 by hardware, the
TXDP has detected an error in the transmit packet header.
0x24C TXDPINTEN – Transmit Data Path Interrupt Enable
BIT
NAME
TYPE
RESET
FUNCTION
31:28
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
27
ERRASYTX
RW
0
Asynchronous transmit error interrupt enable When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding
bit in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
26
ACKLOST
RW
0
Acknowledge lost interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
25
ACKRCVD
RW
0
ACKRCVD interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
24
ERRISOTX
RW
0
ERRISOTX interrupt enable When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
23
ERRBFLSH0
RW
0
ERRBFLSH0 interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
22
ERRBFLSH1
RW
0
ERRBFLSH1 interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
21
ERRBFLSH2
RW
0
ERRBFLSH2 interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.
20
ERRBFLSH3
RW
0
ERRBFLSH3 interrupt enable – When this bit is set to 1, the
SYSINT.TXDPINT1 bit is set to 1 when the corresponding bit in the
TXDPINT register is set by hardware. When set to 0, the corresponding bit
in the TXDPINT register has no effect on the SYSINT.TXDPINT1 bit.