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674
0x34C RXDPINTEN Receive Data Path Interrupt Enables
BIT
NAME
TYPE
RESET
FUNCTION
31:24
PKTRCVERR(N)
RW
0
Packet receive error – When this bit is set to 1, the SYSINT.RXDPINT1
bit is set to 1 when the corresponding bit in the RXDPINT register is set
by hardware. When set to 0, the corresponding bit in the RXDPINT
register has no effect on the SYSINT.RXDPINT1 bit.
23:16
PKTRCVD(N)
RW
0
Packet received When this bit is set to 1, the SYSINT.RXDPINT1 bit
is set to 1 when the corresponding bit in the RXDPINT register is set by
hardware. When set to 0, the corresponding bit in the RXDPINT
register has no effect on the SYSINT.RXDPINT1 bit.
15
EVODCHNGB
RW
0
Even/odd bit change stream B When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
14
EVODCHNGA
RW
0
Even/odd bit change stream A When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
13
EMIERRB
RW
0
Encryption mode indicator error stream B When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
12
EMIERRA
RW
0
Encryption mode indicator error stream A When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
11
DVSPLITERRB
RW
0
Digital video split error stream B When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
10
DVSPLITERRA
RW
0
Digital video split error stream A When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
9
DVSEQERRB
RW
0
Digital video sequence error stream B When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
8
DVSEQERRA
RW
0
Digital video sequence error stream A When this bit is set to 1, the
SYSINT.RXDPINT0 bit is set to 1 when the corresponding bit in the
RXDPINT register is set by hardware. When set to 0, the
corresponding bit in the RXDPINT register has no effect on the
SYSINT.RXDPINT0 bit.
7
RSVD
RW
0
Reserved – A write to this location has no effect. A read returns 0.