![](http://datasheet.mmic.net.cn/390000/TSB42AA4I_datasheet_16839080/TSB42AA4I_36.png)
311
Table 34. Multistrobe Mode Read Critical Timing Numbers
VALUE
MIN
MAX
UNIT
S0 Setup time for address valid to MCIF_CS low
0
S1 Setup time for MCIF_CS low to MCIF_RW(OE) asserted
0
S2 Setup time for MCIF_RW(OE) asserted to beginning of data
0
D0 Delay time from MCIF_RW(OE) asserted to read data operation complete MCIF_ACK
114
nS
H0 Hold time between two MCIF_RW(OE) cycles
9
nS
H1 Hold time between MCIF_RW(OE) high and MCIF_CS high
0
3.2
High-Speed Data Interface (HSDI)
The high-speed data interface is designed to support high-bandwidth applications, where the access
latency of the microcontroller interface is insufficient for the bandwidth of the streaming data. Examples
include MPEG2 or DV streams where the upper limit of the incoming or outgoing data can be up to 60 Mbps.
The HSDI can support throughputs of up to 27 MBps in byte-wide mode, and up to 66 MHz in serial mode.
All supported data types can be transmitted and/or received at this interface, including asynchronous
streams, asynchronous, DVB, DirecTV, and DV type data.
The high-speed data interface consists of two bidirectional, 8-bit data busses; HSDI ports A and B. Each
bus has a corresponding 3-bit address bus used to select the internal FIFO that is to be written or read. The
address bus is used only in multistream mode. HSDIA_A[2:0] determine the FIFO accessed by HSDI port
A, and HSDIB_A[2:0] determine the FIFO accessed by HSDI port B. Each port has its own read and write
control signals. Figure 313 shows the interface signals for each port. In general, the HSDI is a fully
bidirectional interface.
The HSDI has two stream modes: single stream and multistream. In single stream mode, each HSDI port
can only be connected to a maximum of one transmit buffer and one receive buffer. The HSDI accesses the
buffers based on the HSDIx_RW signal.
In multistream mode, each HSDI port can be connected to multiple transmit or receive buffers. The HSDI
determines which buffer to access by decoding the HSDIx_A[2:0] signals. The HSDIx_RW must be used
to determine the interface direction.
The HSDI supports three synchronization modes: Mode A, Mode B and Mode C. The sync mode defines
how the HSDIx_SYNC signal is used to determine packet boundaries on transmit and receive. The
HSDIx_SYNC signal is input on transmit and output on receive.
The HSDIx_EN signal is an input used on transmit to indicate valid data. Data is not written to transmit buffers
unless the HSDIx_EN signal is active. HSDIx_EN is also an input on receive to indicate the application is
ready to receive the data. No data is received by the application until the HSDIx_EN signal is active.
The HSDIx_AV signal is an output used to indicate when data is available for reading. This signal is active
once one cell of data is available in the receive buffer. For data types that use time-stamp based release,
the HSDIx_AV signal is activated only after the timestamp matches the cycle timer. The signal is not used
in transmit mode.
The HSDIx_RW signal is used to indicate the direction of the HSDIx. In multistream mode, the HSDIx_RW
is used with the HSDIx_A[2:0] signals to determine the buffer and the direction of the access. In single
stream mode, the HSDIx_RW signal is used to select the fixed transmit or receive buffer.
All HSDI control signals are programmable in their active level (
active high
or
active low
). The default is
active high
. The endianness of the byte stacking operation is programmable to either big (default) or little
endian independently for transmit and receive mode.