
617
0x044 LINT – Link Interrupts (Continued)
BIT
8
NAME
TYPE
RCU
RESET
0
FUNCTION
PHYBUSRST
PHY bus reset – When this bit is set to 1, the PHY has entered the 1394
bus reset state. An interrupt is generated when the corresponding
enable bit in LINTEN is set. Write 1 to clear.
7
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
6
CYCSEC
RCU
0
Cycle seconds – When set to 1, the cycle seconds field in the cycle timer
register has incremented. An interrupt is generated when the
corresponding enable bit in LINTEN is set. Write 1 to clear.
5
CYCSTART
RCU
0
Cycle start – When set to 1, the link transmitter has sent or the link
receiver has received a cycle start packet. An interrupt is generated
when the corresponding enable bit in LINTEN is set. Write 1 to clear.
4
CYCDONE
RCU
0
Cycle done – When set to 1, a subaction gap has been detected on the
bus after the transmission or reception of a cycle start packet. An
interrupt is generated when the corresponding enable bit in LINTEN is
set. Write 1 to clear.
3:2
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
1
ARBRSTGAP
RCU
0
Arbitration reset gap – This bit is set to 1 when an arbitration reset gap
has been detected. An interrupt is generated when the corresponding
enable bit in LINTEN is set. Write 1 to clear.
0
SUBACTGAP
RCU
0
Subaction gap – This bit is set to 1 when a subaction gap has been
detected. An interrupt is generated when the corresponding enable bit
in LINTEN is set. Write 1 to clear.
0x048 LINTEN – Link Interrupt Enables
BIT
31:22
NAME
TYPE
R0
RESET
0
FUNCTION
RSVD
Reserved – A write to this location has no effect. A read returns 0s.
21
HDRERR
RW
0
Header error interrupt enable– When this bit is set to 1, the
SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT1 bit.
20
SIDERR
RW
0
Self ID error interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT1 bit.
19
ISOARBFL
RW
0
Isochronous arbitration failed interrupt enable – When this bit is set to 1,
the SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the
LINT register is set by hardware. When set to 0, the corresponding bit in
the LINT register has no effect on the SYSINT.LLCINT1 bit.
18
CYCTOOL-
ONG
RW
0
Cycle too long interrupt enable When this bit is set to 1, the
SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT1 bit.
17
CYCLOST
RW
0
Cycle lost interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT1 bit.
16
CYCARBFAIL
RW
0
Cycle arbitration failed interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT1 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT1 bit.
15:11
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.