
Functional Description
(Continued)
18 μs in
≥
10 secs without “slip”, exceeding CCITT recom-
mendation Q.502. Excessive wander causes a controlled
slip of one complete frame.
6.0 DIGITAL INTERFACE DATA FORMATS IN
MICROWIRE MODE (MW = 1)
When the MW pin is tied high to enable the Microwire Port
for control and status, the Digital System Interface on the
TP3410 provides a choice of four multiplexed formats for the
B and D channel data, as shown in Figures 3, 4, 5, 6, 7
These apply in both LT and NT modes of the device, and se-
lection is made via Register CR1. Selection of DSI Master or
Slave mode must also be made in CR1. Within each format
there is also an independent selection available to either
multiplex the D channel (Tx and Rx) data on the same pins
as the B channels, or via the separate D-channel access
pins, DCLK, Dx and Dr, see Section 6.3.
Format 1:
In Format 1, the 2B+D data transfer is assigned
to the first 18 bits of the frame on the Bx and Br
pins. Channels are assigned as follows: B1 (8
bits), B2 (8 bits), D (2 bits), with the remaining
bits ignored until the next frame sync pulse.
When the D channel port is enabled (see CR2),
only the 2 B channels use the Bx and Br pins;
the D bits are assigned to the 17th and 18th bits
of the frame on the Dx and Dr pins. Figure 3
shows this format in DSI Slave Mode, and Fig-
ure 6 shows DSI Master Mode.
Format 2:
Format 2 is the IDL, in which the 2B+D data
transfer is assigned to the first 19 bits of the
frame on the Bx and Br pins. Channels are as-
signed as follows: B1 (8 bits), D (1 bit), 1 bit ig-
nored, B2 (8 bits), D (1 bit), with the remaining
bits ignored until the next frame sync pulse. Fig-
ure 4 shows this format in DSI Slave Mode, and
Figure 7 shows DSI Master Mode.
This format provides time-slot assignment capa-
bility for the B1 and B2 channels, which can be
independently assigned to any 8-bit wide
time-slot from 64 (or less) on the Bx and Br pins;
the Transmit and Receive directions are also in-
dependently assignable.Also the D channel can
be assigned to any 2-bit wide time-slot from 256
(or less) on the Bx and Br pins (D port disabled)
or on the Dx and Dr pins (see D-Channel Port
section). Figure 5 shows this format in DSI
Slave Mode, and Figure 8 shows DSI Master
Mode; see also Section 6.2.
This is similar to the GCI format for the 2B+D
channels, but excludes the Monitor channel and
C/I channel. Channels are assigned to the first
26 bits of each frame as follows: B1 (8 bits), B2
(8 bits), ignored (8 bits), D (2 bits). The remain-
ing bits in the frame are ignored until the next
frame sync pulse. The relationship between
BCLK and data is the same as in the GCI mode
for GCI Channel 0, see Figure 14(in DSI Master
Mode, BCLK = 512 kHz and FS
a
is a square
wave output).
Format 3:
Format 4:
DS009151-5
FSa defines B1 channel for Tx.
FSb defines B1 channel for Rx.
FIGURE 3. DSI Format 1: Slave Mode
9
www.national.com
PrintDate=1997/07/09 PrintTime=13:38:10 1109 ds009151 Rev. No. 1
Proof
9