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參數(shù)資料
| 型號： | TP3410J304 |
| 英文描述： | IC-ISDN TRANSCEIVER |
| 中文描述： | 集成電路- ISDN的收發(fā)器 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 332K |
| 代理商： | TP3410J304 |
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Functional Description
(Continued)
M
SW/ISW =
=
M-channel, bits 235–240 in frame
synchronization word/inverted
synchronization word, bits 1–18 in frame
2.2 Line Transmit Section
Data to be transmitted to the line consists of the customer’s
2B+D channel data and the data from the maintenance pro-
cessor, plus other “spare” bits in the overhead channels.
This data is multiplexed and scrambled prior to addition of
the syncword. A pulse waveform synthesizer then drives the
transmit filter, which in turn passes the line signal to the line
driver. The differential line-driver outputs, Lo+ and Lo, are
designed to drive a transformer through an external termina-
tion circuit. A 1:1.5 transformer, designed as shown in the
Applications section, results in a signal amplitude of nomi-
nally 2.5V pk on the line for single quats of the outer (
±
3) lev-
els. Note, however, that because of the RDS accumulation of
the 2B1Q line code, continuous random data will produce
signal swings considerably greater than this on the line.
Short-circuit protection is included in the output stage; over-
voltage protection must be provided externally.
2.3 Line Receive Section
The receive input signal should be derived from the trans-
former by means of a coupling circuit as shown in the Appli-
cations section. At the front-end of the receive section is a
continuous filter followed by a switched-capacitor low-pass
filter, which limits the noise bandwidth. A Hybrid Balance Fil-
ter provides a degree of analog echo-cancellation in order to
limit the dynamic range of the composite signal. An A/D con-
verter then samples the composite received signal prior to
the cancellation of the “echo” from the local transmitter by
means of an adaptive digital transversal filter (i.e., the
“echo-canceller”). Following this, the attenuation and distor-
tion (inter-symbol interference) of the received signal from
the far-end, caused by the transmission line, are equalized
by a second adaptive digital filter configured as a Decision
Feedback Equalizer (DFE), thereby restoring a “flat” channel
response with maximum received eye opening over a wide
spread of cable attenuation characteristics.
From the received line signal, a Timing Recovery circuit
based on a DPLL (Digital Phase-Locked Loop) recovers a
low-jitter clock for optimum sampling of the received sym-
bols. The MCLK input provides the reference clock for the
DPLLat 15.36 MHz. Received data is then detected, with au-
tomatic correction for line signal polarity if necessary, and a
flywheel synchronization circuit searches for and locks onto
the frame and superframe syncwords. Frame lock will be
maintained until errored sync words are detected for 480 ms.
If a loss-of-sync condition persists for 480 ms the device will
cease transmitting and go into a RESET state.
While the receiver is synchronized, data is descrambled us-
ing the specified polynomial, and the individual channels de-
multiplexed and passed to their respective processing cir-
cuits.
Whenever the loop is deactivated, either powered up or pow-
ered down, a Line Signal Detect circuit is enabled to detect
the presence of an incoming 10 kHz wake-up tone if the
far-end starts to activate the loop. The LSD circuit generates
an interrupt and, if the device is powered down, pulls the
LSD pin low; either of these indicators may be used to alert
an external controller, which must respond with the appropri-
ate commands to initiate the activation sequence (see the
Activation section).
3.0 ACTIVATION CONTROL: OVERVIEW
The TP3410 contains an automatic sequencer for the com-
plete control of the start-up activation sequence specified in
the ANSI standard. Both the “cold-start” and the fast
“warm-start” are supported. Interaction with an external con-
troller requires only Activate Request and Deactivate Re-
quest commands, with the option of inserting breakpoints in
the sequence for additional external control if desired. Auto-
matic control of the “act” and “dea” bits in the M4 bit positions
is provided, along with the specified 40 ms and 480 ms tim-
ers used during deactivation. A 15 second default timer is
also included, to prevent system lock-up in the event of a
failed activation attempt. Section 11 gives an overview of the
activation handshake between the TP3410 and the control-
ler. See TP3410 User’s Manual AN-913 for additional infor-
mation.
4.0 MAINTENANCE FUNCTIONS: OVERVIEW
4.1 M Channel Processing
In each frame of the superframe there are 6 “Overhead” bits
assigned to various control and maintenance functions of the
DSL. Some processing of these bits may be programmed via
the Command Registers, while interaction with an external
controller provides the flexibility to take full advantage of the
maintenance channels. New data written to any of the over-
head bit Transmit Registers is resynchronized internally to
the next available complete superframe or half-superframe,
as appropriate. In addition, the SFS pin may be used to indi-
cate the start of each superframe in 1 direction, see Figure 2
and Register CR2.
7
www.national.com
PrintDate=1997/07/09 PrintTime=13:38:06 1109 ds009151 Rev. No. 1
Proof
7
相關(guān)PDF資料 |
PDF描述 |
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| TP3420J | ISDN Line Interface |
| TP3420N | ISDN Line Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
| TP3420A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
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