參數(shù)資料
型號(hào): TP3410J304
英文描述: IC-ISDN TRANSCEIVER
中文描述: 集成電路- ISDN的收發(fā)器
文件頁(yè)數(shù): 12/32頁(yè)
文件大小: 332K
代理商: TP3410J304
Functional Description
(Continued)
6.4 D Channel Time-Slot Assignment
In addition to B channel TSA, Format 3 allows independent
Time Slot Assignment for the Transmit and Receive D chan-
nels, which may be programmed via Registers TXD and
RXD. As with the B channels, up to 64 time-slots are avail-
able if BCLK = 4.096 MHz, and in addition the 2 D bits may
be assigned, in pairs, to specific bit locations within the
time-slot; that is in bits 1 and 2; 3 and 4; 5 and 6; or 7 and 8.
D channel TSA may be used either with the D channel mul-
tiplexed with the B channel data, or with the separate D
Channel port clocked with BCLK; it cannot be used with the
16 kHz clock option at DCLK.
Summary of DSI Slave Mode
Options
Function
Format Number
2
Tx
B1
Rx
B1
No
Yes
1
Tx
B1
Rx
B1
Yes
Yes
3
4
FSa
Tx
TS0
Rx
TS0
Yes
Yes
Tx
B1
Rx
B1
Yes
No
FSb
Non-Delayed Timing
Delayed Timing
Function
Format Number
2
Yes
1
3
4
Tx and Rx Frames
with
Any Phase
TSA Available
D Port Available
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
No
Yes
Summary of DSI Master Mode
Options
Function
Format Number
2
B1
B2
Delayed
Only
1
3
4
FSa
FSb
FS Formats
B1
B2
Non-
Delayed
and
Delayed
No
Yes
TS0
TS1
Non-
Delayed Delayed
and
Delayed
Yes
Yes
B1
B2
Non-
Only
TSA Available
D Port Available
No
Yes
No
Yes
Note:
All Formats: Tx and Rx frames always aligned.
DS009151-11
FIGURE 9. D-Port Interface Timing Using DCLK in 16 kHz Mode
DS009151-12
FIGURE 10. D-Port Interface Timing Using BCLK Format 1
PrintDate=1997/07/09 PrintTime=13:38:14 1109 ds009151 Rev. No. 1
Proof
12
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