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參數(shù)資料
| 型號(hào)： | TP3410J304 |
| 英文描述： | IC-ISDN TRANSCEIVER |
| 中文描述： | 集成電路- ISDN的收發(fā)器 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 332K |
| 代理商： | TP3410J304 |
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Functional Description
(Continued)
4.2 Embedded Operations Channel
The EOC channel consists of 2 complete 12-bit messages
per superframe, distributed through the M1, M2 and M3 bits
of each half-superframe as shown in Tables 1, 2 Each mes-
sage is composed of 3 fields; a 3-bit address identifying the
message destination, a 1-bit indicator for the data mode, i.e.,
encoded message or raw data, and an 8-bit information byte.
The Microwire port or GCI Monitor Channel provides access
to the complete 12 bits of every message in the TX EOC and
the RXEOC Registers. If one of the defined encoded mes-
sages is received, e.g., Send Corrupted CRC, then the ap-
propriate Command Register instruction must be written to
the device to invoke the function.
4.3 M4 Bits
The M4 bit position of every frame is a transparent channel
in which are transmitted data bits loaded from the M4 Trans-
mit Register TXM4, one byte per superframe. On the receive
side the M4 bits from one complete superframe are sent to a
checking circuit which holds each new M4 byte and com-
pares it against the previous M4 byte(s) for validation prior to
sending it to the RXM4 Receive Register; Register OPR pro-
vides several options for control of this validation.
4.4 Spare M5 And M6 Bits
Overhead bits M5 and M6 in frame 1 (M51 and M61) and M5
in frame 2 (M52) are transparently transmitted from the
Transmit M56 Spare Bit Register to the line. In the receive di-
rection, data from these bit positions is sent to a checking cir-
cuit which holds the new M5/M6 spare bits and compares
them against the previous M5/M6 bits for validation prior to
sending them to the Receive M56 Spare Bit Register; the
OPR Register provides several options for control of this
validation.
4.5 CRC Circuit
In the transmit direction an on-chip crc calculation circuit au-
tomatically generates a checksum of the 2B+D+M4 bits us-
ing the polynomial x12+x11+x3+x2+x+1. Once per super-
frame the crc is transmitted in the specified M5 and M6 bit
positions (see Tables 1, 2). In the receive direction a check-
sum is again calculated on the same bits as they are re-
ceived and, at the end of the superframe, compared against
the crc transmitted with the data. The result of this compari-
son generates a “Far End Block Error” bit (the febe bit),
which is transmitted back towards the other end of the DSL
in the next superframe. If there are no errors in a super-
frame, febe is set = 1, and if there is one or more errors febe
is set = 0.
The TP3410 also includes a readable 8-bit Block Error
Counter BEC1, which is decremented by 1 each superframe
in which febe = 0 or nebe = 0 is received. Section 10.5 de-
scribes the operation of this counter.
On first application of power, and after the software reset
(X’1880, X’1800), both the ECT1 as well as BEC1 are initial-
ized to X’FF. See the Block Error Counter section for more
details.
5.0 DIGITAL INTERFACE: ALL FORMATS
5.1 Clocking
In LT applications (network end of the Loop), the Digital Sys-
tem Interface (DSI) normally accepts BCLK and FS signals
from the network, requiring the selection of DSI or GCI Slave
mode in Register CR1. A Digital Phase-Locked Loop (DPLL
#
2) on the TP3410 allows the MCLK frequency to be plesio-
chronous (i.e. free-running) with respect to the network
clocks, (BCLK and the 8 kHz FSa input). With a tolerance on
the MCLK oscillator of 15.36 MHz
±
100 ppm, the lock-in
range of DPLL2 allows the network clock frequency to devi-
ate up to
±
50 ppm from nominal.
In NT applications, when the device is in NT mode and is
slaved to loop timing recovered from the received line signal,
DSI or GCI Master mode should normally be selected. In this
case BCLK, FS and SCLK (15.36 MHz) signals are outputs
which
are
phase-locked
to
slave-slave mode is also provided, however, in which the
Digital Interface data buffers on the TP3410 allow BCLK and
FSa/b to be input from an external source, which must be
frequency-locked (but may take an arbitrary phase) to the re-
ceived line signal; in this case DSI or GCI Slave mode
should be selected.
the
recovered
clock.
A
5.2 Data Buffers
The TP3410 buffers the 2B+D data at the Digital Interface in
elastic FIFOs, which are 3 frames deep in each direction.
When the Digital Interface is a timing slave these FIFOs
compensate for relative jitter and wander between the Digital
Interface clocks (BCLK and FSa/b) and bit and frame timing
at the Line Interface. Each buffer can absorb wander up to
DS009151-26
FIGURE 2. Superframe Sync Pin Timing
PrintDate=1997/07/09 PrintTime=13:38:08 1109 ds009151 Rev. No. 1
Proof
8
www.national.com
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3420J | ISDN Line Interface |
| TP3420N | ISDN Line Interface |
| TP3421J | ISDN Line Interface |
| TP3421N | ISDN Line Interface |
| TP3451J | Protocol Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
| TP3420A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
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