參數(shù)資料
型號(hào)： TP3410J304
英文描述： IC-ISDN TRANSCEIVER
中文描述： 集成電路- ISDN的收發(fā)器
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 332K
代理商： TP3410J304
Functional Description
(Continued)
TFB0
*
TFB0 = 1 (default state)
TFB0 = 0 forces transmit febe to 0 continuously for test pur-
poses. TFB0 = 1 allows normal operation controlled by LFS
and RFS. Note that this function was controlled by the TFB
bit in TXM56 register in Rev. 2.x devices. The TFB bit in
TXM56 bit is now (Rev. 3.x) active for one superframe only:
if set to 0 by software, a superframe will transmit febe = 0,
and then the TFB will be reset to 1 by the device. The soft-
ware does not need to set it to 1.
RFS: Remote Febe Select
*
RFS =1 (default state)
The state of the outgoing bit is computed based on the state
of the TFB (bit 1) in TXM56 register. The TFB blt is set=0 by
the software to allow a febe blt from an adjacent DSL to be
forwarded to the next section in the next superframe. This bit
is self resetting (to 1) in Rev. 3.x devices. This is a change
from the Rev. 2.x devices. If RFS=0, then the outgoing febe
does not depend on the state of the TFB blt in TXM56 regis-
ter.
LFS: Local Febe Select
*
LFS =1 (default state)
The state of the outgoing febe bit is computed using the in-
coming nebe blt. If LFS = 0, the outgoing febe is not depen-
dent on the incoming nebe.
Example of use:
A flexible control of the outgoing febe bit is provided to sup-
port the Segmented and Path Performance Monitoring rec-
ommendations in Bellcore TR 397.
For Rev. 2.8 type operation, set RFS = 1, LFS = 1 and TFB0
= 1. This setting will cause the transmit febe to be computed
as OR of the incoming nebe blt and the state of the TFB bit
in TXM56 (representing the adjacent section febe to be for-
warded).
9.7 Configuration Registers TXB1, TXB2, RXB1,
RXB2: B Channel TSA
These registers are effective only when Format 3 is selected.
TXB1 assigns the Transmit time slot for the B1 channel.
TXB2 assigns the Transmit time slot for the B2 channel.
RXB1 assigns the Receive time slot for the B1 channel.
RXB2 assigns the Receive time slot for the B2 channel.
Register TXB1
Byte 2
7
6
5
4
3
2
1
0
0
0
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X'00.
Register TXB2
Byte 2
7
6
5
4
3
2
1
0
0
0
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X'01.
Register RXB1
Byte 2
7
6
5
4
3
2
1
0
EB1
ED
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X'00.
Register RXB2
Byte 2
7
6
5
4
3
2
1
0
EB2
0
TS5
TS4
TS3
TS2
TS1
TS0
*
At Power-On Reset this register is initialized to X'01.
B Channels Time-Slot Assignment: TS5–TS0
The TS5–TS0 bits define the binary number of the time-slot
when the B channel selected is shifted to or from the Bx and
Br pins; time-slots are numbered from 0 to 63. New time-slot
assignments become effective only at the beginning of a
frame.
B1 and D Channel Enables: EB1; ED
*
EB1=0 to disable the B1 channel; B1 is high-impedance at
Br.
EB1 = 1 to enable the B1 channel (must also set DD=0 in
CR2).
*
ED = 0 to disable the D channel; D is high-impedance at Br
or Dr.
ED = 1 to enable the D channel (must also set DD=0 in
CR2).
B2 Channel Enable: EB2
EB2 = 0 to disable the B2 channel; B2 is high-impedance at
Br.
EB2 = 1 to enable the B2 channel (must also set DD=0 in
CR2).
9.8 Configuration Register TXD:
Transmit D Channel TSA
This register is effective only when Format 3 is selected. D
channel TSA may be used when the D channel is accessed
either via the Bx/Br or Dx/Dr pins, but the D channel port
must be clocked with BCLK (DMO = 0 in CR2).
Byte 2
7
6
5
4
3
2
1
0
DX5
DX4
DX3
DX2
DX1
DX0
SX1
SX0
*
At Power-On Reset this register is initialized to X'08.
Transmit D Channel Time-Slot Assignment Select:
DX5–DX0, SX1–SX0
DX5–DX0 bits define the binary number of the 8-bit wide
time-slot, where time-slots are numbered from 0 to 63.
Within this selected time-slot, the SX1 and SX0 bits define
the 2-bit wide sub-slot for the 2 D channel bits. Sub-slots are
numbered 0 to 3, as shown in Figures 10, 11, 12 Figure 18
and Figure 19 and the following table. New time-slot and
sub-slot assignments become effective only at the beginning
of a frame.
Sub-Slot
Bit Positions
within Time-Slot
1, 2
3, 4
SX1
*
0
0
SX0
0
1
PrintDate=1997/07/09 PrintTime=13:38:33 1109 ds009151 Rev. No. 1
Proof
20
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參數(shù)描述
TP3410J-304 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP
TP3410J304/NOPB 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410J304-X 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410N304 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP
TP3420A 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device
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