參數(shù)資料
型號(hào)： TP3410J304
英文描述： IC-ISDN TRANSCEIVER
中文描述： 集成電路- ISDN的收發(fā)器
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 332K
代理商： TP3410J304
Functional Description
(Continued)
9.0 COMMAND REGISTER FUNCTIONS
All addressing and bit-level functions are the same for
both the Microwire and GCI Monitor Channels, except
where noted. Register addresses are listed in Table 3 An
asterisk
*
indicates the Power-on Reset state of each
function. The device modes and Transmit M bits should be
programmed while the device is powered down.
9.1 Writing to Command Registers
A command may be written to a register to modify its con-
tents by setting byte 1 bit 0=0. Registers CR1, 2, 3, OPR
and the Time-SlotAssignment registers may also be read-
back to verify the contents by addressing each register
with byte 1 bit 0=1. In Microwire Mode, if the device has
no data waiting to be read during a command cycle it will
return X'0000 (No Change).
9.2 Reading Back Command Registers for
Verification
To read back the current state of one of the write-able reg-
isters, the appropriate readback command must first be
loaded in via the control channel; this will cause an inter-
rupt to be sent to the interrupt stack. In Microwire mode
the interrupt must be serviced by a read cycle, in which
the command should be a NOP (or a new command). In
this cycle the previously addressed register is read back,
with byte 1 bit 0=1. In GCI mode, the interrupt stack gen-
erates an autonomous one-way message in the Monitor
Channel. If any other interrupt conditions should occur
during the readback command cycle, the readback result
will be queued at the bottom of the stack, and will not gen-
erate its interrupt or message until all other interrupts are
cleared.
9.3 Configuration Register CR1: Digital Interface
Byte 2
7
6
5
4
3
2
1
0
FF1
FF0
CK2
CK1
CK0
DDM
CMS
BEX
*
CR1 is set to X'00 at Power-On Reset.
FF1, FF0: Digital System Interface Frame Format
Selection
These bits are effective in Microwire Mode only (MW=1).
They select the Digital Interface format as described in Sec-
tion 6.
Format
*
1
2
3
4
FF1
0
0
1
1
FF0
0
1
0
1
CK0–CK2: Digital Interface Clock Select
In Microwire Mode only, and if DSI Master is selected (CMS
= 1), CK0–CK2 bits select from a choice of 5 frequencies for
the BCLK output. (In GCI Mode, these bits have no effect.)
The frequency of 256 kHz is not valid with Format 4.
CK2
0
0
CK1
0
0
CK0
0
1
BCLK Frequency:
*
256 kHz Master
512 kHz Master
CK2
0
0
1
CK1
1
1
0
CK0
0
1
0
BCLK Frequency:
1536 kHz Master
2048 kHz Master
2560 kHz Master
DDM: Delayed Data Mode Select
For Microwire mode, see Section 6.1: FS Relationship to
Data. In GCI Mode or Format 4 this bit has no effect.
*
DDM = 0 for non-delayed data mode (see Figure 18).
DDM = 1 for delayed data mode (see Figure 19).
CMS: DSI Clock Master/Slave Select
In Microwire Mode (MW = 1):
CMS = 0 for DSI Slave; may be used in either LT or NT
Modes
CMS = 1 for DSI Master; may be used in either LT or NT
Modes, but when in LT Mode, must also send X'1840. See
the TP3410 User’s Manual AN-913 Section 4.5 for details.
In GCI Mode (MW = 0) this bit has no effect; the MO pin se-
lects GCI Master or Slave.
BEX: B Channel Exchange
This command enables the two B channels to be exchanged
as the data passes through the device between the Digital
Interface and the Line in both directions. It should not be
used if any loopback is selected in the device.
*
BEX = 0 for B channels mapped direct, B1 to B1 and B2 to
B2.
BEX = 1 for B channels exchanged, B1 to B2 and B2 to B1.
9.4 Configuration Register CR2: Device Modes
Byte 2
7
6
5
4
3
2
1
0
SSS
NTS
DMO
DEN
DD
BP1
BP2
0
*
CR2 is set to X'00 at Power-On Reset.
SSS: Superframe Synchronization Select
This bit is effective in LT mode only; in NT mode the SFS pin
is an output. When SSS = 0, SFS is an input which synchro-
nizes the transmit superframe counter on the line.
When SSS = 1, SFS is an output superframe marker pulse.
NTS: NT or LT Select
*
NTS = 0 for LT Mode.
NTS = 1 for NT Mode.
DEN: D Channel Port Select
*
When DEN = 0, the D channel port is disabled and the D
bits are transferred on the Br and Bx pins, clocked by BCLK.
The Dx pin must also be tied to GND for correct operation.
When DEN = 1, the D channel port is enabled; D bits are
transferred on the Dr and Dx pins in a mode selected by the
DMO bit, see Section 6.3.
DMO: D Channel Transfer Mode Select
This bit is significant only when the D channel port is se-
lected (DEN bit = 1).
When DMO = 1, D channel data is shifted in and out on Dx
and Dr pins in a continuous mode at 16 kbit/s on the falling
and rising edges of DCLK respectively, see Figure 9
PrintDate=1997/07/09 PrintTime=13:38:28 1109 ds009151 Rev. No. 1
Proof
18
www.national.com
18
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參數(shù)描述
TP3410J-304 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP
TP3410J304/NOPB 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410J304-X 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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TP3420A 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:ISDN S/T Interface Device
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