
Functional Description
(Continued)
6.1 FS Relationship To Data (Microwire Mode)
For applications on a line-card, in DSI Slave Mode, the B and
D channel slots can be interfaced to a Time-Division Multi-
plexed (TDM) bus and assigned to a time-slot. The repetition
rate of the FS input signals must be 8 kHz and must be syn-
chronized to the BCLK input, which may be any frequency
from 256 kHz to 4.096 MHz in 8 kHz increments. Two differ-
ent relationships may be established between the FS inputs
and the actual time-slots on the PCM busses by setting the
DDM bit in Control Register CR1, see Figures 3, 4, 5, 6, 7
Figure 18 and Figure 19 Non-delayed data mode is similar
to long frame timing on the TP3050/60 series of devices
(COMBO I): the time-slots are defined by the 8-bit duration
FSa and FSb signals. The alternative is to use Delayed Data
Mode, which is similar to short frame sync timing on COMBO
I, in which each FS input indicates the start of the first
time-slot.
Serial B channel data is shifted into the Bx input during each
assigned Transmit time-slot on the falling edges of BCLK.
During each assigned Receive time-slot, the Br output shifts
data out on the rising edges of BCLK.Also, with the device in
LT Mode, the TS r pin is an open drain n-channel pull-down
output which goes low during the selected time-slots for the
received B1 and B2 channels at the Br pin to control the
TRI-STATE
Enable
of
a
high-impedance at all other times.
In NT Mode, when DSI Master mode is selected, FSa and
FSb are outputs indicating the B1 (or TS0) and the B2 (or
TS1) channels respectively. BCLK is also an output at the
serial data shift rate, which is dependent on the format se-
backplane
line-driver;
it
is
lected. Again, either a delayed or non-delayed relationship
between FSa, FSb and the start of the first time-slot can be
selected.
6.2 B Channel Time-slot Assignment; Format 3 Only
(Microwire Mode)
In Format 3 only, the TP3410 provides programmable
time-slot assignment for selecting the Transmit and Receive
B channel time-slots. Following power-on, the device is auto-
matically in Non-delayed Data Mode; if Delayed Data Mode
is required it must first be selected (see CR1) prior to using
Time-slot Assignment, and the FS pulses must conform to
the Delayed Data timing format. The actual transmit and re-
ceive time-slots are then determined by the internal
Time-slot Assignment counters, programmed via Control
Registers TXB1, TXB2, RXB1 and RXB2. Normally used in
DSI Slave mode, Format 3 allows a frame to consist of up to
64 time-slots of 8 bits each with BCLK up to 4.096 MHz.
A new assignment becomes active on the second frame fol-
lowing the end of the 16-bit Chip Select.
6.3 D Channel Port Selection (Microwire Mode)
In any of the DSI Formats, the 2 D channel bits per frame
may either be multiplexed with the B channels on the Bx and
Br pins, or may be accessed via the separate D channel port
consisting of Dx and Dr. Furthermore, when using the sepa-
rate D port the data shift clock may either be a continuous,
unframed data stream using the 16 kHz clock output at
DCLK, see Figure 9 or may use the BCLK, see Figures 10,
11, 12 Selection of these options is via Control Register
CR2.
DS009151-9
FIGURE 7. DSI Format 2 (IDL): Master Mode
DS009151-10
Transmit and Receive slots are numbered relative to FSa.
FIGURE 8. DSI Format 3: Master Mode
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PrintDate=1997/07/09 PrintTime=13:38:12 1109 ds009151 Rev. No. 1
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