- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365894 > TP3410J304 IC-ISDN TRANSCEIVER PDF資料下載
參數(shù)資料
| 型號： | TP3410J304 |
| 英文描述： | IC-ISDN TRANSCEIVER |
| 中文描述： | 集成電路- ISDN的收發(fā)器 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 332K |
| 代理商： | TP3410J304 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Functional Description
(Continued)
controller to provide the interface for the microcontroller to
access the EOC Registers. To use the device in an NT-1 or
Regenerator, a microcontroller is required and Microwire
mode should be used on the TP3410.
8.1 GCI Physical Interface
The interface physically consists of four wires:
— Transmit data to line:
— Receive data from line: Br
— Bit clock at 2 cycles/bit: BCLK
— 8 kHz frame sync:
Data is synchronized by the BCLK and FSa clock inputs.
FSa insures re-initialization of the time-slot counter at the be-
ginning of each 8 kHz frame, with the rising edge of FSa be-
ing the reference time for the first GCI channel bit. Data is
clocked in both directions at half the BCLK input frequency.
Data bits are output from the device on a rising edge of
BCLK and sampled on the second falling edge of BCLK; un-
used slots are high impedance. Br is an open-drain
n-channel output, with internal detection for contention reso-
lution on the Monitor and C/I channels between devices at-
tempting to use the same GCI channel (typically in a TE ap-
plication).
Adevice may be either the Master or Slave of the GCI timing.
As a Master it is the source of BCLK, FSa and FSb, which
Bx
FSa
are synchronized to the data received from the line, and GCI
channel 0 is always used. As a GCI Slave, BCLK and FSa
must be sourced externally, typically from a system back-
plane, and pins S0–S2 must be connected high or low to se-
lect the required GCI channel. To use the single channel
mode, a 512 kHz BCLK is required, and S2, S1 and S0 must
be connected to GND (GCI Channel 0). To use the multiplex
mode with a GCI Slave device, the 4 pins are commoned be-
tween up to 8 devices, forming a “wire-AND” connection with
the Br pins. The BCLK frequency must be at least n x 512
kHz, where n is the number of devices. In fact BCLK may be
operated up to 6144 kHz if required, to leave up to 4 addi-
tional GCI channels unoccupied by TP3410’s (and available
for other uses). Clock and channel selection are shown in
the following table:
Pin Name
MW
MO
S2/CLS
LT and NT1–2
0
0 (GCI Slave)
S2 (msb)
NT1 and TE
0
1 (GCI Master)
CLS=0: 512 kHz
CLS=1: 1536 kHz
0
FSb
S1
S1
S0/FSb
S0 (lsb)
8.2 GCI Frame Structure
Figure 14 shows the frame structure at the GCI interface.
One GCI channel supports one TP3410 using a bandwidth
of 256 kbit/s, consisting of the following channels multi-
plexed together in an 8 kHz frame:
—
B1 channel at 8 bits per frame;
—
B2 channel at 8 bits per frame;
—
Monitor (M) channel at 8 bits per frame;
—
Signalling and Control (SC) channel, which is structured
as follows:
D Channel at 2 bits per frame;
C/I channel at 4 bits per frame;
A bit, for acknowledgement of M channel bytes;
E
bit,
which
indicates
multiple-byte messages are transferred via the M chan-
nel.
byte
boundaries
when
8.3 Monitor Channel
The GCI Monitor channel (byte 3) is used to access all the
Command Registers shown in Table 3 with the exception of
the Activation Control Register, and all the Status Registers
shown in Table 4 with the exception of the Activation Indica-
tion Register. Each access to or from one of the listed regis-
ters requires a 2-byte message transfer. As shown in Table 3
and Table 4 the first byte from the originating device con-
tains the register address, and the second byte is the data
byte. Status Registers originate messages in the Monitor
channel under control of the Interrupt Stack (in the same
manner as when the TP3410 is used in Microwire Mode). In
addition a protocol is used, based on the E and A bits in byte
4, to provide an acknowledgement of each Monitor channel
byte in either direction, see Figure 15
When no Monitor Channel message is being transferred, the
E bit, and the A bit in the reverse direction, are
high-impedance (and pulled high by the external resistor if
no other device is active in that channel). To initiate a trans-
fer, a device must first verify that it has received the A bit=1
for at least 2 consecutive GCI frames from the other device
DS009151-15
FIGURE 13. Microwire Control Port Timing: MW = 1
PrintDate=1997/07/09 PrintTime=13:38:18 1109 ds009151 Rev. No. 1
Proof
14
www.national.com
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3420J | ISDN Line Interface |
| TP3420N | ISDN Line Interface |
| TP3421J | ISDN Line Interface |
| TP3421N | ISDN Line Interface |
| TP3451J | Protocol Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
| TP3420A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
發(fā)布緊急采購，3分鐘左右您將得到回復。