參數(shù)資料
型號(hào)： TP3410J304
英文描述： IC-ISDN TRANSCEIVER
中文描述： 集成電路- ISDN的收發(fā)器
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 332K
代理商： TP3410J304
Functional Description
(Continued)
11.7 NT Mode Activation/Deactivation
If activation is initiated by the upstream (LT mode) end with
the NT either powered up or down, a Line Signal Detect In-
terrupt will be generated on detection of the 10 kHz
“wake-up” tone. The Activation Indication Register will show
this condition and, if the device is powered down, the LSD
pin will be pulled low. To proceed with the activation se-
quence, all registers must be programmed appropriately
(see Note 1) and the device must then be powered up. The
use of the commands and status indicators is the same
whether activation is initiated locally or in response to the
Line Signal Detect Interrupt. An AR command will enable the
device to automatically proceed with the activation se-
quence. An internal 15s default timer is also started (in North
America the timer value should be 15 seconds if a single
DSL section is being activated). See TP3410 User’s Manual
for additional information on activation and deactivation.
The sequence continues until the NT acquires superframe
synchronization on the SL2 signal received from the LT. At
this point an AP Interrupt is generated and the device starts
transmitting SN3 with “act” = 0. To complete activation, nor-
mally when the NT has detected INFO3 signals from a TE,
the “act” bit must be set = 1 by writing the AC command to
the Activation Control Register. An AI Status indication will fi-
nally be generated by the device when the loop is fully syn-
chronized and receiving SL3 frames with “act”=1; this is au-
tomatically validated 3 times regardless of the options
selected in Register OPR. The loop is then fully activated,
with all channels in the data stream available for use.
If activation is not successfully completed before expiry of
the 15s timer, the device generates an EI followed by a DI
fault indication and ensures that the Activation Sequencer
returns to the Full Reset state prior to any re-attempt to ac-
tivate.
Deactivation is normally initiated by the LT, which sets
“dea”=0 towards the NT. The TP3410 in NT mode will detect
and validate this bit 3 times prior to setting the DP interrupt
(regardless of the options selected in OPR). Transmission
will cease when it is detected that the far-end signal has
ceased, after which the device enters the Reset state and
generates a DI Interrupt to indicate that deactivation is com-
plete.
Note:
The M45 bit conveys an indication of whether the NT can support a
warm-start procedure (the “cso” bit). Since the TP3410 automatically
supports both cold and warm start, set “cso”=0.
Applications Information
LINE INTERFACE CIRCUIT
The transmission performance obtainable from a TP3410
U-interface is strongly dependent on the line interface circuit
(LIC) design. Two designs, shown in Figure 16 and Figure
17 are recommended. They should be adhered to strictly.
The channel response and insertion losses of these circuits
have been carefully designed as an integral part of the over-
all signal processing system to ensure the performance re-
quirements are met under all specified loop conditions. De-
viations from these designs may result in sub-optimal
performance or even total failure of the system to operate on
some types of loops.
The standare LIC (Figure 16) has the advantage of back-
wards compatibility with Rev. 2.x devices together with a
generally lower component sensitivity. The TP3410 must be
configured to select the chosen LIC. For the standard LIC,
set saif = 1 in register CR4. This is the default configuration.
The alternative LIC (Figure 17) does not use lineside surge
limiting resistors and so has advantages where line power-
ing is required. To configure the TP3410 for the alternative
LIC, set saif = 0.
Transformer parameters form a major part of the LIC. Two of
the most important are:
Turns Ratio:
Chip side (primary): Line side (secondary)
= 1:1.5
Secondary inductance:
L
S
= 27 mH
±
5% at 1 kHz
For more details on transformer specification and for a list of
qualified vendors, see the TP3410 User’s Manual, AN-913.
BOARD LAYOUT
While the pins of the TP3410 are well protected against elec-
trical misuse, it is recommended that the standard CMOS
practice of applying GND to the device before any other con-
nections are made should always be followed. In applica-
tions where the printed circuit card may be plugged into a hot
socket with power and clocks already present, an extra long
ground pin on the connector should be used.
Great care must be taken in the layout of the printed circuit
board in order to preserve the high transmission perfor-
mance of the TP3410. To maximize performance do not use
the philosophy of separating analog and digital grounds on
the board. The 3 GND pins should be connected together as
close as possible to the pins, and the 2 V
pins should be
strapped together. All ground connections to each device
should meet at a common point as close as possible to the 3
GND pins in order to prevent the interaction of ground return
currents flowing through a common bus impedance. A de-
coupling capacitor of 0.1 μF should be connected from this
common point to the V
pins. Taking care with the pcb lay-
out in the following ways will also help prevent noise injection
into the receiver front-end and maximize the transmission
performance:
1.
Keep the crystal oscillator components away from the
receiver inputs and use a ground plane for shielding
around these components.
2.
Keep the connections between the device and the com-
ponents on the Li
±
inputs short.
3.
Keep the connections between the device and trans-
former short.
ADDITIONAL INFORMATION
For more in-depth information on a variety of applications,
the TP3410 Users Manual, AN-913, is a comprehensive
guide to the hardware and software required to meet the
ANSI interface specification.
25
www.national.com
PrintDate=1997/07/09 PrintTime=13:38:45 1109 ds009151 Rev. No. 1
Proof
25
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP3410J-304 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP
TP3410J304/NOPB 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410J304-X 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410N304 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP
TP3420A 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device
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